ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet
ADC1112D125F2/DB,598
Specifications of ADC1112D125F2/DB,598
Related parts for ADC1112D125F2/DB,598
ADC1112D125F2/DB,598 Summary of contents
Page 1
Quick start ADC1412D, ADC1212D, ADC1112D series Demonstration board for ADC1412D, ADC1212D, ADC1112D series Rev. 10 — 17 December 2010 Document information Info Content Keywords PCB2004-1, Demonstration board, ADC, Converter, ADC1412D, ADC1212D and ADC1112D series. Abstract This document describes how to ...
Page 2
... NXP Semiconductors Revision history Rev Date Description 1 20081001 Initial version. 2 20090518 Update to PCB2004-1.2. 3 20090610 Add SPI software description. 4 20100518 Update to latest release of SPI software. Add HSDC extension module acquisition system description. 5 20100601 Correction added. 6 20100730 Update for LVDS acquisition mode. 7 20100806 Update to latest acquisition software tool ...
Page 3
Overview of the ADC1412D, ADC1212D, ADC1112D demo board 1.1 ADC1412D series Figure 1 presents the connections to measure the ADC1412D series: P OWER SUPPLY SYNTHESIZED . I = 370 mA SIGNAL GENERATOR I A NPUT SIGNAL F ILTER . ...
Page 4
ADC1212D series Figure 2 presents the connections to measure the ADC1212D series: P OWER SUPPLY SYNTHESIZED . I = 370 mA SIGNAL GENERATOR I A NPUT SIGNAL F ILTER . 2 V sinewave . High-order ...
Page 5
ADC1112D series Figure 3 presents the connections to measure the ADC1112D series: P OWER SUPPLY SYNTHESIZED . I = 370 mA SIGNAL GENERATOR I A NPUT SIGNAL F ILTER . 2 V sinewave . High-order ...
Page 6
... NXP Semiconductors 1.4 Power supply The board is powered with regulator is used to supply all the circuitry on the board. Table 1. General power supply Name Function green connector – Power supply +1.8 V green connector – Power supply 1.8 V TP1 AGND test point – Digital ground TP2 DGND test point – ...
Page 7
... NXP Semiconductors 1.6 Output signals (DA0 to DA13, DB0 to DB13, OTRA, DAV) The digital output signal is available in binary, 2’s complement or gray format. A Data Valid Output clock (DAV) is provided by the device for the data acquisition. Table 3. Output signals Name Function J5 Array connector – ADC A digital output(DA0 to DA13), ...
Page 8
HSDC extension module: acquisition board The figure 4 shows an overview of the extension module HSDC-EXTMOD01/DB acquisition board: RED LED FOR +3V3 POWER SIGNAL GENERATOR R EFERENCE SIGNAL . typical 10 MHz GREEN LED FOR EMBEDDED PLL LOCK STATUS ...
Page 9
... NXP Semiconductors The HSDC extension module is intended for acquisition/generation and clock generation purpose. When connected to an ADC demo-board it is intended as an acquisition system for digital output bits delivered by ADC, either CMOS (HE14 P1 connector) or LVDS DDR (SAMTEC QTH_060_02 P2 connector). The board brief specification is shown below memory size for acquisition pattern ...
Page 10
... NXP Semiconductors Fig 5. HSDC extension module: HE14 CMOS hardware schematic overview QS_ADC1412D_10.doc Quick start Quick start ADC1412D, ADC1212D, ADC1112D series Rev. 10 — 17 December 2010 Quick start © NXP B.V. 2010. All rights reserved ...
Page 11
Combo ADC1412D and HSDC extension module 3.1 ADC1412D CMOS outputs (demoboard F1/DB) The figure 6 below shows an overview of the whole system ADC1412D+HSDC extension module with CMOS outputs configuration (e.g. ADC1412D125F1/DB) for which connection is straightforward, together with ...
Page 12
ADC1412D LVDS outputs (demoboard F2/DB) The figure 7 below shows an overview of the whole system ADC1412D+HSDC extension module with LVDS outputs configuration (e.g. ADC1412D125F1/DB) for which connection is done with a bridge SAMTEC (HSDC-ACC05/DB), together with a supply ...
Page 13
... NXP Semiconductors 3.3 ADC Software tool Run the application “SW_ADC_1_r02.exe”. This application will allow: the user to control features on our high speed ADC through the SPI interface available on any ADC1412D, ADC1212D and ADC1112D series; as well as performing any online data acquisition to evaluate the performances of the ADC1412D, ADC1212D and ADC1112D series ...
Page 14
... NXP Semiconductors Fig 9. SW_ADC_1_r02: “Info” page The HSDC-EXTMOD is not yet initialized, so the embedded PLL (LMK03001 in this example) is not locked. Initialization is only required for acquisition purpose. 3.3.1 ADC SPI programming Functional Registers page The page displays all SPI registers for ADC1412D, ADC1212D and ADC1112D series: Fig 10. SW_ADC_1_r02: “ ...
Page 15
... NXP Semiconductors Perform any settings and then click on the “Send data to device” button to update the device registers. 3.3.2 ADC SPI programming Read Registers page This page can be used to read all registers by clicking on the “Read all registers” button and will display the result in the table below: Fig 11. SW_ADC_1_r02: “ ...
Page 16
... NXP Semiconductors Column Note that all data are saved in hexadecimal format. Click on the “Save registers read to file” button to select the file to store data to. Make sure that you store your file with “.txt” extension, this will allow you to re-use the file on the “ ...
Page 17
... NXP Semiconductors Table 6. Content of file is shown as table format Column 1 Register Name Channel index Reset and operating mode Clock Internal reference Output data standard Output clock Offset Test pattern 1 Test pattern 2 Test pattern 3 Fast OTR CMOS output LVDS DDR O/P 1 LVDS DDR O/P 2 Note that all data are saved in hexadecimal format ...
Page 18
... NXP Semiconductors Fig 13. SW_ADC_1_r02: “ADC - Load Registers” page It is not necessary to have a file that has the whole set of registers listed. The only restriction is regarding the formatting of the file as given in Note: this page can not be used to download data saved during the comparison process. ...
Page 19
... NXP Semiconductors Fig 14. SW_ADC_1_r02: “Tools” page Note: The level of the harmonics shown does not reproduce the behavior of the ADC; they are only given as indication for location. 3.3.6 Acquisition page This page will acquire data to evaluate the high dynamic performance of the device: Fig 15. SW_ADC_1_r02: “ ...
Page 20
... NXP Semiconductors Before proceeding to any acquisition, the user needs to do the following entries: the sampling frequency Fs: 80 Msps in our example (field the input frequency Fin: 175 MHz in our example for both ADC channels (field the number of samples to be acquired 16384 in our example (field indicate whether it is CMOS or LVDS DDR (field press the “ ...
Page 21
... NXP Semiconductors Fig 16. SW_ADC_1_r02: “Acquisition” page, FFT graph Press the “Autoscale” button to display the whole content. 3.3.6.2 Reorganized signal The reorganized signal displays the reconstructed sine wave from coherency calculation corresponding to 1 period of the input signal: Fig 17. SW_ADC_1_r02: “Acquisition” page, reorganized signal graph QS_ADC1412D_10 ...
Page 22
... NXP Semiconductors Press the “Autoscale” button to display the whole content. 3.3.6.3 Unreconstruted signal The unreconstructed signal displays the unreconstructed sine wave corresponding to the whole number of period being acquired following the coherency rule: Fig 18. SW_ADC_1_r02: “Acquisition” page, unreconstructed signal graph Press the “ ...
Page 23
... NXP Semiconductors Fig 19. SW_ADC_1_r02: “Acquisition” page, code histogram graph Press the “Autoscale” button to display the whole content. The table shows the range of output codes. 3.3.7 Info page This page will give practical information related to software and hardware settings: Fig 20. SW_ADC_1_r02: “Info” page QS_ADC1412D_10 ...
Page 24
... NXP Semiconductors The information visible on this page are: board serial number HSDC software release number HSDC-EXTMOD dll version HSDC-EXTMOD vhdl version HSDC-EXTMOD supply status HSDC-EXTMOD clock capability and status version HSDC-EXTMOD memory capability QS_ADC1412D_10.doc Quick start Quick start ADC1412D, ADC1212D, ADC1112D series ...
Page 25
... NXP Semiconductors 4. Appendix A.1: coherency calculation The coherency relies on the fact that clock and analog input signal are synchronized and the first and last samples being captured are adjoining samples: it ensures a continuous digitized time process for the FFT processing. To achieve this, one has to follow the equation: where odd integer equal to the number of periods being acquired and N the number of samples acquired ...
Page 26
... NXP Semiconductors 5. Notes For any question, feel free to contact us at the following e-mail support@nxp.com. QS_ADC1412D_10.doc Quick start Quick start ADC1412D, ADC1212D, ADC1112D series Rev. 10 — 17 December 2010 Quick start dataconverter- © NXP B.V. 2010. All rights reserved ...
Page 27
... NXP Semiconductors 6. Contents 1. Overview of the ADC1412D, ADC1212D, ADC1112D demo board ......................................3 1.1 ADC1412D series ..............................................3 1.2 ADC1212D series ..............................................4 1.3 ADC1112D series ..............................................5 1.4 Power supply......................................................6 1.5 Input signals (IN, CLK) .......................................6 1.6 Output signals (DA0 to DA13, DB0 to DB13, OTRA, DAV).......................................................7 1.7 SPI Mode ...........................................................7 1.8 SPI program .......................................................7 2 ...