ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet
ADC1112D125F2/DB,598
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ADC1112D125F2/DB,598 Summary of contents
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ADC1112D125 Dual 11-bit ADC; CMOS or LVDS DDR digital outputs Rev. 2 — 3 March 2011 1. General description The ADC1112D125 is a dual channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption. Pipelined architecture ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s ADC1112D125HN/C1 125 5. Block diagram Fig 1. Block diagram ADC1112D125 Product data sheet Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Name Description HVQFN64 plastic thermal enhanced very thin quad flat package; ...
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... NXP Semiconductors 6. Pinning information 6.1 CMOS outputs selected 6.1.1 Pinning Fig 2. 6.1.2 Pin description Table 2. Symbol INAP INAM AGND VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT ADC1112D125 Product data sheet Dual 11-bit ADC: CMOS or LVDS DDR digital outputs terminal 1 ...
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... NXP Semiconductors Table 2. Symbol VCMB AGND INBM INBP VDDA VDDA SCLK/DFS SDIO/ODS CS CTRL DECB OTRB DB10 DB9 DB8 DB7 DB6 DB5 VDDO VDDO DB4 DB3 DB2 DB1 DB0 n.c. n.c. n.c. n.c. DAV n.c. n.c. n.c. DA0 DA1 DA2 VDDO VDDO ...
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... NXP Semiconductors Table 2. Symbol DA9 DA10 OTRA DECA VDDA SENSE VREF VDDA [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. 6.2 LVDS DDR outputs selected 6.2.1 Pinning Fig 3. ADC1112D125 Product data sheet Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Pin description (CMOS digital outputs) ...
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... NXP Semiconductors 6.2.2 Pin description Table 3. Symbol DB9_DB10_M DB9_DB10_P DB7_DB8_M DB7_DB8_P DB5_DB6_M DB5_DB6_P DB3_DB4_M DB3_DB4_P DB1_DB2_M DB1_DB2_P LOW_DB0_M LOW_DB0_P n.c. n.c. DAVM DAVP n.c. n.c. LOW_DA0_P LOW_DA0_M DA1_DA2_P DA1_DA2_M DA3_DA4_P DA3_DA4_M DA5_DA6_P DA5_DA6_M DA7_DA8_P DA7_DA8_M DA9_DA10_P DA9_DA10_M [1] Pins 1 to 24, pin and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs ...
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... NXP Semiconductors 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter DDA V DDO T stg T amb Thermal characteristics Table 5. Symbol R th(j-a) R th(j-c) [1] Value for six layers board in still air with a minimum of 64 thermal vias. 9. Static characteristics Table 6 ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter Clock inputs: pins CLKP and CLKM Low-Voltage Positive Emitter-Coupled Logic (LVPECL) V differential clock input voltage i(clk)dif Sine V differential clock input voltage i(clk)dif Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) V LOW-level input voltage IL V HIGH-level input voltage ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter B input bandwidth i V differential input voltage I(dif) Common-mode output voltage: pins VCMA and VCMB V common-mode output voltage O(cm) I common-mode output current O(cm) I/O reference voltage: pin VREF V voltage on pin VREF VREF Accuracy INL integral non-linearity ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Dynamic characteristics Symbol Parameter Analog signal processing α second harmonic level 2H α third harmonic level 3H THD total harmonic distortion ENOB effective number of bits SNR signal-to-noise ratio SFDR spurious-free dynamic range IMD Intermodulation distortion α ...
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... NXP Semiconductors 10.2 Clock and digital output timing Table 8. Clock and digital output timing characteristics Symbol Parameter Clock timing input: pins CLKP and CLKM f clock frequency clk t data latency time lat(data) δ clock duty cycle clk t sampling delay time d(s) t wake-up time ...
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... NXP Semiconductors Fig Fig 5. ADC1112D125 Product data sheet Dual 11-bit ADC: CMOS or LVDS DDR digital outputs d(s) t clk CLKP CLKM − 14) DATA DAV clk clk CMOS mode timing d(s) t clk CLKP CLKM t (N − 14 x+ x DAVP DAVM t clk ...
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... NXP Semiconductors 10.3 SPI timings Table 9. Symbol SPI timings t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V across the full temperature range T Fig 6. ADC1112D125 Product data sheet Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Characteristics Parameter SCLK pulse width SCLK HIGH pulse width ...
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... NXP Semiconductors 10.4 Typical characteristics 3.2 C (pF) 3.0 2.8 2.6 2.4 50 150 250 Fig 7. Capacitance as a function of frequency 100 SFDR (dBc ° 170 MHz (1) DCS on (2) DCS off Fig 9. SFDR as a function of duty cycle (δ) ADC1112D125 Product data sheet Dual 11-bit ADC: CMOS or LVDS DDR digital outputs ...
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... NXP Semiconductors 92 SFDR (dBc) (1) ( −40 °C/typical supply voltages (1) T amb = +25 °C/typical supply voltages (2) T amb = +90 °C/typical supply voltages (3) T amb Fig 11. SFDR as a function of duty cycle (δ) 90 SFDR (dBc 0.5 1.0 1.5 2.0 Fig 13. SFDR as a function of common-mode input voltage (V ...
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... NXP Semiconductors 11. Application information 11.1 Device control The ADC1112D125 can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up and remains in this mode as long as pin CS is held HIGH ...
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... NXP Semiconductors 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. ...
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... NXP Semiconductors Fig 17. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. Input frequency (MHz) 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Fig 18. Single transformer configuration suitable for baseband applications The configuration shown in both cases, the choice of transformer is a compromise between cost and performance ...
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... NXP Semiconductors Fig 19. Dual transformer configuration suitable for high intermediate frequency 11.3 System reference and power management 11.3.1 Internal/external references The ADC1112D125 has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable steps between 0 dB and − ...
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... NXP Semiconductors VREF SENSE Fig 20. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 12. Selection Internal (Figure Internal (Figure External (Figure Internal via SPI (Figure [1] The voltage on pin VREF is doubled internally to generate the internal reference voltage. ...
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... NXP Semiconductors VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 21. Internal reference (p-p) full-scale VREF 0.1 μF V SENSE VDDA Fig 23. External reference (p- (p-p) full-scale 11.3.2 Programmable full-scale The full-scale is programmable between 1 V (p- (p-p) (see Table 13. INTREF 000 001 010 011 100 101 ...
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... NXP Semiconductors VCMA/VCMB Fig 25. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (V set externally to 0.5V and 2 V (see 11.4 Clock input 11.4.1 Drive modes The ADC1112D125 can be driven differentially (LVPECL). It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a capacitor) ...
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... NXP Semiconductors a. Sine clock input c. LVPECL clock input Fig 27. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via internal 5 kΩ resistors. Fig 28. Equivalent input circuit ADC1112D125 Product data sheet ...
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... NXP Semiconductors Single-ended or differential clock inputs can be selected via the SPI interface (see Table control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performance of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = logic 1 ...
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... NXP Semiconductors The output resistance is 50 Ω and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see 11 ...
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... NXP Semiconductors Table 14. LVDS_INT_TER[2:0] 000 001 010 011 100 101 110 111 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1112D125. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in recommended to shift ahead the DAV (bits DAVPHASE[2:0] = 0b100 ...
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... NXP Semiconductors 11.5.6 Test patterns For test purposes, the ADC1112D125 can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see can be defined by the user (TESTPAT_USER[10:3]; see TESTPAT_USER[2:0]; see The selected test pattern is transmitted regardless of the analog input. 11.5.7 Output codes versus input voltage Table 16. − ...
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... NXP Semiconductors Table 17. Bit Description [1] Bit R/W indicates whether read (logic write (logic 0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred (see Table 18 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses ...
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... NXP Semiconductors When the ADC1112D125 enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] (see Fig 33. Default mode at start-up: SCLK LOW = offset binary ...
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Register allocation map Table 19. Register allocation map Address Register name Access (hex) Bit 7 0003 Channel index R/W 0005 Reset and R/W SW_ operating mode RST 0006 Clock R/W - 0008 Internal reference R/W - 0011 Output data ...
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... NXP Semiconductors Table 20. Channel index control register (address 0003h) bit description Default values are highlighted. Bit Symbol RESERVED[5:0] 1 ADCB 0 ADCA Table 21. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit Symbol 7 SW_RST RESERVED[2: OP_MODE[1:0] Table 22. ...
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... NXP Semiconductors Table 23. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol INTREF_EN INTREF[2:0] Table 24. Output data standard control register (address 0011h) bit description Default values are highlighted. Bit Symbol LVDS_CMOS 3 OUTBUF 2 OUTBUS_SWAP DATA_FORMAT[1:0] ADC1112D125 Product data sheet ...
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... NXP Semiconductors Table 25. Output clock register (address 0012h) bit description Default values are highlighted. Bit Symbol DAVINV DAVPHASE[2:0] [ clk clk Table 26. Offset register (address 0013h) bit description Default values are highlighted. Bit Symbol DIG_OFFSET[5:0] Table 27. Test pattern 1 register (address 0014h) bit description Default values are highlighted ...
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... NXP Semiconductors Table 28. Test pattern 2 register (address 0015h) bit description Default values are highlighted. Bit Symbol TESTPAT_USER[10:3] Table 29. Test pattern 3 register (address 0016h) bit description Default values are highlighted. Bit Symbol TESTPAT_USER[2: Table 30. Fast OTR register (address 0017h) bit description Default values are highlighted. ...
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... NXP Semiconductors Table 32. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit Symbol RESERVED DAVI[1:0] 2 RESERVED DATAI[1:0] Table 33. LVDS DDR output register 2 (address 0022h) bit description Default values are highlighted. Bit Symbol BIT_BYTE_WISE LVDS_INT_TER[2:0] ADC1112D125 Product data sheet ...
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... NXP Semiconductors 12. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 0.85 mm terminal 1 index area terminal 1 64 index area Dimensions Unit max 1.00 0.05 0.30 mm nom 0.85 0.02 0.21 0.2 min 0.80 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 34. Acronym ADC CMOS DAV DCS DFS ESD FS IMD LSB LVCMOS LVDS DDR LVPECL MSB OTR SFDR SNR SPI TX ADC1112D125 Product data sheet Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Abbreviations Description Analog-to-Digital Converter Complementary Metal Oxide Semiconductor ...
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... NXP Semiconductors 14. Revision history Table 35. Revision history Document ID ADC1112D125 v.2 Modifications: ADC1112D125 v.1 ADC1112D125 Product data sheet Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Release date Data sheet status 20110303 Product data sheet • Data sheet status changed from Preliminary to Product. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Dual 11-bit ADC: CMOS or LVDS DDR digital outputs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 CMOS outputs selected . . . . . . . . . . . . . . . . . . 3 6.1.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 LVDS DDR outputs selected 6.2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Thermal characteristics ...