DS2408S+ Maxim Integrated Products, DS2408S+ Datasheet - Page 4

• Manufacturer Part Number: DS2408S+
• Description: PROM 1-Wire 8-Ch Addressable Switch
• Manufacturer: Maxim Integrated Products

Specifications of DS2408S+

• Lead Free Status / Rohs Status: Details

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: The earliest recognition of a negative edge is possible at t
Note 12: Highlighted numbers are NOT in compliance with the published 1-Wire standards. See
Note 13: Interval during the negative edge on I/O at the beginning of a presence detect pulse between
Note 14: e represents the time required for the pullup circuitry to pull the voltage on I/O up from V
Note 15: d represents the time required for the pullup circuitry to pull the voltage on I/O up from V
Note 16: Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between
Note 17: Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset
Note 18: Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.
1)
t
t
t
t
t
t
PARAMETER
SLOT
RSTL
PDH
PDL
W0L
SLS
Intentional change, longer recovery-time requirement due to modified 1-Wire front end.
, t
NAME
(incl. t
SPD
System Requirement
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an
active pullup such as that found in the DS2480B may be required.
If a 2.2kW resistor is used to pull up the data line to V
the parasite capacitance does not affect normal communications.
Guaranteed by design—not production tested.
V
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to V
low.
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After V
detected as logic '0'.
before.
comparison table below.
the time at which the voltage is 90% of V
V
to V
to the input high threshold of the bus master.
the time at which the voltage is 90% of V
V
(for the RSTZ pin). For a pulse duration t
t
pulse will be recognized and latched.
No requirement for current balance among different pins.
PWMIN(min)
REC
TL
PUP
PUP
, V
TH
.
. PIO pullup resistor = 2.2kW.
)
.
TH
TH
are a function of the internal supply voltage.
480µs
MIN
61µs
15µs
60µs
60µs
15µs
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
< t
STANDARD
PW
SPEED
< t
STANDARD VALUES
PWMIN(max)
(undef.)
(undef.)
240µs
120µs
MAX
60µs
60µs
, the pulse may or may not be rejected. If t
MIN
48µs
OVERDRIVE
2µs
8µs
6µs
2µs
7µs
SPEED
4 of 36
(undef.)
PUP
PUP
PW
MAX
80µs
24µs
16µs
6µs
6µs
: If t
and the time at which the voltage is 10% of
and the time at which the voltage is 10% of
PW
ILMAX
< t
65µs
660µs
MIN
15µs
60µs
60µs
15µs
PUP
PWMIN(min)
STANDARD
whenever the master drives the line
, 5µs after power has been applied,
REH
SPEED
1)
after V
DS2408 VALUES
(undef.)
, the pulse will be rejected. If
720µs
280µs
120µs
MAX
60µs
60µs
TH
has been reached
PW
> t
1.8µs
MIN
10µs
53µs
OVERDRIVE
2µs
7µs
8µs
PWMIN(max)
SPEED
HY
(undef.)
MAX
80µs
27µs
13µs
7µs
8µs
the
to be
IL
IL