DS2408S+ Maxim Integrated Products, DS2408S+ Datasheet - Page 8

• Manufacturer Part Number: DS2408S+
• Description: PROM 1-Wire 8-Ch Addressable Switch
• Manufacturer: Maxim Integrated Products

Specifications of DS2408S+

• Lead Free Status / Rohs Status: Details

Figure 5. DS2408 REGISTER ADDRESS MAP
PIO Logic-State Register
The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers
command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as
PIO Logic State Register Bitmap
This register is read-only. Each bit is associated with the pin of the respective PIO channel as shown in
Figure 6. The data in this register is sampled at the last (most significant) bit of the byte that proceeds
reading the first (least significant) bit of this register. See the Read PIO Registers command description
for details.
PIO Output Latch State Register
The data in this register represents the latest data written to the PIO through the Channel-access Write
command. This register is read using the Read PIO Registers command. Reading this register does not
generate a signal at the RSTZ pin, even if it is configured as
description for details on
hit.
PIO Output Latch State Register Bitmap
This register is read-only. Each bit is associated with the output latch of the respective PIO channel as
shown in Figure 6.
The flip-flops of this register will power up in a random state. If the chip has to power up with all PIO
channels off, a LOW pulse must be generated on the RSTZ pin, e.g., by means of an open-drain CPU
supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure that
RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0).
STRB
ADDRESS RANGE
0000h to 0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh to 008Fh
ADDR
0088h
ADDR
0089h
. See the Channel-Access commands description for details on
PL7
P7
b7
b7
PL6
P6
b6
b6
ACCESS TYPE
STRB
PL5
R/W
R/W
R/W
P5
b5
b5
. This register is not affected if the device reinitializes itself after an ESD
R
R
R
R
R
PL4
P4
b4
b4
DESCRIPTION
Undefined Data
PIO Logic State
PIO Output Latch State Register
PIO Activity Latch State Register
Conditional Search Channel Selection Mask
Conditional Search Channel Polarity Selection
Control/Status Register
These Bytes Always Read FFh
PL3
P3
b3
b3
8 of 36
PL2
P2
b2
b2
STRB
PL1
P1
b1
b1
. See the Channel-access commands
STRB
.
PL0
b0
P0
b0