MAX5971BETI+ Maxim Integrated Products, MAX5971BETI+ Datasheet - Page 31

• Manufacturer Part Number: MAX5971BETI+
• Description: Hot Swap & Power Distribution IEEE 802.3af/at PSE Controller
• Manufacturer: Maxim Integrated Products

Specifications of MAX5971BETI+

• Lead Free Status / Rohs Status: Details

The pin status register (R11h, Table 17) records the state
of the OSC, LEGACY, and MIDSPAN pins. The states
of OSC, LEGACY, and MIDSPAN are latched into the
corresponding bits after a power-up or reset condition
clears. Therefore, the default state of the pin status reg-
ister depends on those inputs (0000 to xxx1). Changes
to those inputs during normal operation are ignored and
do not change the register contents.
Table 17. Pin Status Register
Table 18. Mode Register
Table 19. Port Operating Mode Status
MIDSPAN
SYMBOL
Reserved
Reserved
Reserved
Reserved
Reserved
SYMBOL
Reserved
Reserved
Reserved
Reserved
POFF_CL
Reserved
LEGACY
OSC
MODE
P_M
00
01
10
11
To ADDRESS = 11h
ADDRESS = 12h
BIT NO.
BIT NO.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
______________________________________________________________________________________
TYPE
TYPE
R/W
R/W
R/W
—
—
—
—
—
—
—
—
—
—
R
R
R
Auto (Automatic)
DESCRIPTION
Pin Status Register (R11h)
Semiautomatic
Shutdown
Manual
Reserved
Reserved
Reserved
Reserved
OSC input latched-in status
LEGACY input latched-in status
MIDSPAN input latched-in status
Reserved
Reserved
Reserved
Reserved
Reserved
A logic-high prevents power-up after a classification failure (I > 50mA, valid only in auto mode)
Reserved
MODE[1] for the port
MODE[0] for the port
Single-Port, 40W, IEEE 802.3af/at,
PSE Controller with I
The mode register (R12h, Table 18) contains two bits that
set the MAX5971B mode of operation. Table 19 details
how to set the mode of operation for the device. On a
power-up or after a reset condition, the mode register is
set to a default value of 03h. Use software to program
the mode of operation. The software port specific reset
using RESET_P (R1Ah[0], Table 27) does not affect the
mode register. Setting POFF_CL (R12h[3]) to 1 prevents
power-up after a classification failure.
Configuration Registers (R12h to R17h)
DESCRIPTION
DESCRIPTION
Mode Register (R12h)
2
C
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