MAX5971BETI+ Maxim Integrated Products, MAX5971BETI+ Datasheet - Page 41

• Manufacturer Part Number: MAX5971BETI+
• Description: Hot Swap & Power Distribution IEEE 802.3af/at PSE Controller
• Manufacturer: Maxim Integrated Products

Specifications of MAX5971BETI+

• Lead Free Status / Rohs Status: Details

Table 40. Register Summary
INTERRUPTS
EVENTS
STATUS
CONFIGURATION
ADDR REGISTER NAME
0Ah
0Bh
0Ch
0Dh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
Interrupt
Interrupt Mask
Power Event
Power Event CoR
Detect Event
Detect Event CoR
Fault Event
Fault Event CoR
Startup Event
Startup Event CoR
Supply Event
Supply Event CoR
Port Status
Reserved
Reserved
Reserved
Power Status
Pin Status
Operating Mode
Disconnect Enable
Det/Class Enable
Backoff Enable
Timing
Configuration
Miscellaneous
Configurations 1
______________________________________________________________________________________
R/W
CoR
CoR
CoR
CoR
CoR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
R
R
R
R
R
R
R
R
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SUP_INT
RSRT[1]
INT_EN
MASK7
BIT 7
TSD
Single-Port, 40W, IEEE 802.3af/at,
CLASS[2]
RSRT_EN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RSRT[0]
BIT 6
TSTART[1] TSTART[0] TFAULT[1] TFAULT[0] TDISC[1]
IMAX_INT
CLASS[1]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MASK5
BIT 5
PSE Controller with I
CLASS_EN
V
CLASS[0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PG_CHG
LD_DISC
CL_END
ACD_EN
PGOOD
CL_INT
MASK4
EE_UVLO
BIT 4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
POFF_CL
Reserved
Reserved
Reserved
Reserved
DET_INT
MASK3
V
BIT 3
EE_OV
OSC
DET_ST[2] DET_ST[1] DET_ST[0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CL_DISC
LEGACY
LD_INT
MASK2
V
BIT 2
EE_UV
MIDSPAN
Reserved PWEN_CHG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OUT_ISO
PG_INT
MASK1
P_M[1]
BIT 1
IMAX_FLT
DET_END
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TDISC[0]
HP_TIME
PWR_EN
DCD_EN
BCKOFF
DET_EN
PE_INT
MASK0
P_M[0]
BIT 0
RESET
STATE
0000 to
1010 to
0000 to
0000 to
0000 to
0000 to
0000 to
0000 to
0000 to
0000 to
000x to
0001 to
0000 to
0000 to
1100 to
0000
0100
0000
0000
0000
0000
0000
0000
0011
000x
0001
000x
0000
0000
xxx1
2
—
—
—
—
C
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