DS92LV1021AMSA National Semiconductor, DS92LV1021AMSA Datasheet

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... In addition, the embedded clock guarantees a Block Diagrams TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2003 National Semiconductor Corporation transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Fur- thermore, you may put the DS92LV1021A output pins into TRI-STATE ® ...

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Block Diagrams (Continued) Functional Description The DS92LV1021A is an upgrade to the DS92LV1021. The DS92LV1021A no longer has a power-up sequence require- ment. Like the DS92LV1021, the DS92LV1021A is a 10-bit Serializer designed to transmit data over a differential back- ...

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... The device enters Powerdown when the PWRDN pin is driven low on the Serializer. In Ordering Information Order Number NSID DS92LV1021AMSA Powerdown, the PLL stops and the outputs go into TRI- STATE, disabling load current and reducing supply current into the milliamp range. To exit Powerdown, PWRDN must be driven high ...

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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage −0. CMOS/TTL Output Voltage −0. Bus LVDS Receiver Input Voltage Bus LVDS Driver Output Voltage Bus LVDS Output Short ...

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Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Transmit Clock Period TCP t Transmit Clock High Time TCIH t Transmit Clock Low Time TCIL t TCLK Input Transition CLKT Time ...

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AC Timing Diagrams and Test Circuits FIGURE 1. “Worst Case” Serializer ICC Test Pattern FIGURE 2. Serializer Bus LVDS Output Load and Transition Times Timing shown for TCLK_R/F = LOW www.national.com FIGURE 3. Serializer Input Clock Transition Time FIGURE 4. ...

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AC Timing Diagrams and Test Circuits FIGURE 5. Serializer TRI-STATE Test Circuit and Timing FIGURE 6. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays (Continued) 20026909 7 20026925 www.national.com ...

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AC Timing Diagrams and Test Circuits www.national.com (Continued) FIGURE 7. SYNC Timing Delays FIGURE 8. Serializer Delay 8 20026926 20026911 ...

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AC Timing Diagrams and Test Circuits For an explanation of the Ideal Crossing Point, please see the Application Information Section. FIGURE 9. Serializer Deterministic Jitter and Ideal Crossing Point Application Information DIFFERENCES BETWEEN THE DS92LV1021A AND THE DS92LV1021 The DS92LV1021A ...

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... In point-to-point configurations the trans- mission media need only be terminated at the receiver end. In the point-to-point configuration the potential of offsetting the ground levels of the Serializer vs. the Deserializer must be considered. Bus LVDS provides a plus / minus one volt common mode range at the receiver inputs. DS92LV1021AMSA - Serializer 20026918 10 ...

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Serializer Pin Description Pin Name I/O DIN I TCLK_R/F I DO+ O DO− O DEN I PWRDN I TCLK I SYNC I DVCC I DGND I AVCC I AGND I Truth Table DIN (0–9) TCLK_R/F TCLK ...

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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) Order Number DS92LV1021AMSA NS Package Number MSA28 2. A critical component is any component of a life ...