DS92LV1021AMSA National Semiconductor, DS92LV1021AMSA Datasheet - Page 5

• Manufacturer Part Number: DS92LV1021AMSA
• Manufacturer: National Semiconductor

Specifications of DS92LV1021AMSA

• Number Of Elements: 1
• Number Of Receivers: 10
• Number Of Drivers: 1
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Output Type: Serializer
• Differential Output Voltage: 270mV
• Transmission Data Rate: 400Mbps
• Power Dissipation: 1.27W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP-EIAJ
• Lead Free Status / Rohs Status: Not Compliant

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCP
TCIH
TCIL
CLKT
JIT
LLHT
LHLT
DIS
DIH
HZD
LZD
ZHD
ZLD
SPW
PLD
SD
BIT
DJIT
Symbol
Symbol
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: t
DJIT
Bus LVDS
Low-to-High
Transition Time
Bus LVDS
High-to-Low
Transition Time
DIN (0-9) Setup to
TCLK
DIN (0-9) Hold from
TCLK
DO
TRI-STATE Delay
DO
TRI-STATE Delay
DO
HIGH Delay
DO
LOW Delay
SYNC Pulse Width
Serializer PLL Lock
Time
Serializer Delay
Bus LVDS Bit Width
Deterministic Jitter
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition
Time
TCLK Input Jitter
specifications are Guranteed By Design (GBD) using statistical analysis.
±
±
±
±
Parameter
HIGH to
LOW to
TRI-STATE to
TRI-STATE to
Parameter
CC
C
= 3.3V and T
L
=10pF to GND,
R
(Note 5)
L
= 27Ω,
Figure 8 , R
Figure 5 ,(Note 4),
C
C
C
C
A
Conditions
L
L
L
L
= +25˚C.
=10pF to GND
=10pF to GND
=10pF to GND
=10pF to GND
Conditions
R
R
R
R
R
R
Figure 2,
Figure 4,
Figure 7,
Figure 6,
L
L
L
L
L
L
= 27Ω,
= 27Ω,
= 27Ω,
= 27Ω,
= 27Ω
= 27Ω
L
= 27Ω
f = 40 MHz
f = 16 MHz
5
0.4T
0.4T
Min
25
510*t
t
TCP
5*t
−320
−800
Min
4.0
0
TCP
+1.0
TCP
0.5T
0.5T
Typ
T
3
t
TCP
t
CLK
−110
−160
0.31
0.30
Typ
3.5
2.9
2.5
2.7
+ 2.0
/ 12
Max
62.5
0.6T
0.6T
2049*t
150
t
TCP
6
Max
0.75
0.75
150
380
10
10
10
10
+4.0
TCP
www.national.com
(RMS)
Units
Units
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps