PC28F512P30EFA Micron Technology Inc, PC28F512P30EFA Datasheet - Page 69

• Manufacturer Part Number: PC28F512P30EFA
• Manufacturer: Micron Technology Inc

Specifications of PC28F512P30EFA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: BGA
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

P30-65nm
Table 40: Partition Region 1 Information (Sheet 2 of 2
Datasheet
69
P=10Ah
(P+2C)h
(P+2D)h
(P+3A)h
(P+3B)h
(P+3C)h
(P+3D)h
(P+2E)h
(P+2F)h
(P+30)h
(P+31)h
(P+32)h
(P+33)h
(P+34)h
(P+35)h
(P+36)h
(P+37)h
(P+38)h
(P+39)h
(P+3E)h
(P+3F)h
(P+40)h
(P+41)h
(P+42)h
(P+43)h
(P+44)h
(P+45)h
Offset
Partition Region 1 Erase Block Type 1 Information
Partition 1 (Erase Block Type 1)
Partition 1 (erase block Type 1) bits per cell; internal EDAC
Partition 1 (erase block Type 1) page mode and synchronous mode capabilities defined in Table
10
Partition Region 1 (Erase Block Type 1) Programming Region Information
Partition Region 1 Erase Block Type 2 Information
Partition 1 (Erase Block Type 2)
Partition 1 (erase block Type 2) bits per cell; internal EDAC
Partition 1 (erase block Type 2) page mode and synchronous mode capabilities defined in Table
10
Partition Region 1 (Erase Block Type 2) Programming Region Information
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5-7 = reserve for future use
bits 0-15 = y, y+1 = # identical-size erase blks in a partition
bits 16-31 = z, region erase block(s) size are z x 256 bytes
bits 0-3 = bits per cell in erase region
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitted (1=yes, 0=no)
bits 3-7 = reserved for future use
bits 0-7 = x, 2^x = Programming Region aligned size (bytes)
bits 8-14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16-23 = y = Control Mode valid size in bytes
bits 24-31 = Reserved
bits 32-39 = z = Control Mode invalid size in bytes
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
bits 0-15 = y, y+1 = # identical-size erase blks in a partition
bits 16-31 = z, region erase block(s) size are z x 256 bytes
Block erase cycles x 1000
bits 0-3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5-7 = reserve for future use
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
bits 0-7 = x, 2^x = Programming Region aligned size (bytes)
bits 8-14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16-23 = y = Control Mode valid size in bytes
bits 24-31 = Reserved
bits 32-39 = z = Control Mode invalid size in bytes
bits 40-46 = Reserved;
bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
Block erase cycles x 1000
(Optional flash features and commands)
Description
Order Number:208042-05
Len
4
2
1
1
6
4
2
1
1
6
Apr 2010
Addr.
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13B:
13C:
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14C:
14D:
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13E:
13F:
140:
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