IDT74ALVCHR16501PA IDT, Integrated Device Technology Inc, IDT74ALVCHR16501PA Datasheet

IDT74ALVCHR16501PA

Manufacturer Part Number
IDT74ALVCHR16501PA
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT74ALVCHR16501PA

Logic Family
ALVC
Operating Supply Voltage (typ)
2.5/3.3V
Propagation Delay Time
7.3ns
Number Of Elements
1
Number Of Channels
18
Input Logic Level
LVTTL
Output Logic Level
LVTTL
Output Type
3-State
Package Type
TSSOP
Polarity
Non-Inverting
Logical Function
Universal Bus Transceiver
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
3.6V
Quiescent Current (typ)
100nA
Technology
CMOS
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical t
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• V
• V
• CMOS power levels (0.4μ μ μ μ μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low Switching Noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
IDT74ALVCHR16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
machine model (C = 200pF, R = 0)
CC
CC
CC
= 3.3V ± 0.3V, Normal Range
= 2.5V ± 0.2V
= 2.7V to 3.6V, Extended Range
SK(o)
(Output Skew) < 250ps
CLKAB
CLKBA
OEAB
LEBA
OEBA
LEAB
A
1
28
30
1
55
2
27
3
3.3V CMOS 18-BIT UNIVERSAL
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
CLK
1D
C1
TO 17 OTHER CHANNELS
1
DESCRIPTION:
CMOS technology. Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB
is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/
flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs
are active. When OEAB is low, the outputs are in the high-impedance state. Data
flow from B to A is similiar to that of A to B but uses OEBA, LEBA, and CLKBA.
The output enables are complementary (OEAB is active high and OEBA is active
low).
will significantly reduce reduce line noise when used with light loads. This driver
has been designed to drive ±12mA at the designated threshold levels.
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
This 18-bit universal bus transceiver is built using advanced dual metal
The ALVCHR16501 has series resistors in the device output structure which
The ALVCHR16501 has “bus-hold” which retains the inputs’ last state
1D
C1
CLK
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCHR16501
54
B
1
JANUARY 2004
DSC-4613/3

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IDT74ALVCHR16501PA Summary of contents

Page 1

... OUTPUTS AND BUS-HOLD DESCRIPTION: This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high ...

Page 2

... IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS PIN CONFIGURATION OEAB 1 2 LEAB GND GND GND GND OEBA LEBA 28 TSSOP TOP VIEW ABSOLUTE MAXIMUM RATINGS Symbol (2) V TERM (3) V TERM 56 GND T STG 55 CLKAB I OUT GND NOTES Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause ...

Page 3

... IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS FUNCTION TABLE (1,2) Inputs OEAB LEAB CLKAB ↑ ↑ NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, and CLKBA HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ ...

Page 4

... IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS BUS-HOLD CHARACTERISTICS (1) Symbol Parameter I Bus-Hold Input Sustain Current BHH I BHL I Bus-Hold Input Sustain Current BHH I BHL I Bus-Hold Input Overdrive Current BHHO I BHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. ...

Page 5

... IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SWITCHING CHARACTERISTICS Symbol Parameter t Propagation Delay PLH PHL t Propagation Delay PLH t LEBA LEAB to Bx PHL t Propagation Delay PLH t CLKBA CLKAB to Bx PHL t Output Enable Time PZH OEBA PZL t Output Enable Time ...

Page 6

... IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 LZ V 300 300 OUT (1, 2) Pulse D.U.T. Generator R T Test Circuit for All Outputs DEFINITIONS Load capacitance: includes jig and probe capacitance. ...

Page 7

... IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS ORDERING INFORMATION IDT ALVC X XXX XX Family Temp. Range Bus-Hold CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXX Device Type Package PA Thin Shrink Small Outline Package 501 18-Bit Universal Bus Transceiver with 3-State Outputs Double-Density, ± ...

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