TDA9109A STMicroelectronics, TDA9109A Datasheet - Page 34

• Manufacturer Part Number: TDA9109A
• Manufacturer: STMicroelectronics

Specifications of TDA9109A

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Supplier Unconfirmed

TDA9109A
3 VERTICAL PART
3.1 Function
When the synchronization pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor, C
the typical free running frequency is 100Hz.
The typical free running frequency can be calculat-
ed by:
fo(Hz) = 1.5
A negative or positive TTL level pulse applied on
Pin 2 (VSYNC) as well as a TTL composite sync
on Pin 1 can synchronize the ramp in the range
[fmin, fmax] (See Figure 16). This frequency range
depends on the external capacitor connected on
Pin 22. A 150nF ( 5%) capacitor is recommended
for 50Hz to 185Hz applications.
If a synchronization pulse is applied, the internal
oscillator is synchronized immediately but with
wrong amplitude. An internal correction then ad-
justs it in less than half a second. The top value of
the ramp (Pin 22) is sampled on the AGC capaci-
tor (Pin 20) at each clock pulse and a transcon-
ductance amplifier modifies the charge current of
the capacitor in such a way to make the amplitude
constant again.
The read status register provides the vertical Lock-
Unlock and the vertical sync polarity information.
We recommend the use of an AGC capacitor with
low leakage current. A value lower than 100nA is
mandatory.
A good stability of the internal closed loop is
reached by a 470nF
20 (VAGC).
34/47
.
10
-5 .
C
OSC
1
5% capacitor value on Pin
OSC
= 150nF,
3.2 I
S and C correction shapes can then be added to
this ramp. These frequency-independent S and C
corrections are generated internally. Their ampli-
tudes are adjustable by their respective I
ters. They can also be inhibited by their "select"
bits.
Finally, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp ampli-
tude control register.
The adjusted ramp is available on Pin 23 (V
drive an external power stage.
The gain of this stage can be adjusted ( 25%) de-
pending on its register value.
The mean value of this ramp is driven by its own
I
VPOS = 7/16
Usually V
the inverting input of the booster. Since VPOS de-
rives from V
inverting input of the booster should also derive
from V
cation Diagram).
3.3 Vertical Moiré
By using the vertical moiré, VPOS can be modulat-
ed from frame to frame. This function is intended
to cancel the fringes which appear when the line to
line interval is very close to the CRT vertical pitch.
The amplitude of the modulation is controlled by
register VMOIRE on sub-address 0C and can be
switched-off via the control bit D8.
2
C register (vertical position). Its value is
2
C Control Adjustments
REF-V
OUT
REF-V
to optimize the accuracy (see Appli-
.
is sent through a resistive divider to
V
REF-V
, the bias voltage sent to the non-
400mV.
2
C regis-
OUT
) to