E28F016SA-100 Intel, E28F016SA-100 Datasheet - Page 16

• Manufacturer Part Number: E28F016SA-100
• Manufacturer: Intel

Specifications of E28F016SA-100

• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F016SA
4.4
16
Read Extended
Status Register
Page Buffer Swap
Read Page Buffer
Single Load to Page
Buffer
Sequential Load to
Page Buffer
Page Buffer Write to
Flash
Two-Byte Program
Lock Block/Confirm
Upload Status
Bits/Confirm
Upload Device
Information
Erase All Unlocked
Blocks/Confirm
RY/BY# Enable to
Level-Mode
RY/BY# Pulse-On-
Write
RY/BY# Pulse-On-
Erase
RY/BY# Disable
Sleep
Abort
ADDRESS
BA = Block Address
PBA = Page Buffer Address
RA = Extended Register Address
PA = Program Address
X = Don’t Care
Command
28F016SA–Performance Enhancement Command Bus Definitions
Mode
x16
x16
x8
x8
x8
4,5,6,10
3,4,9,10
Notes
4,6,10
4,5,10
11
1
7
3
2
8
8
8
8
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
SEE NEW DESIGN RECOMMENDATIONS
First Bus Cycle
Addr
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Data
xx0CH
xx0CH
xxFBH
xxE0H
xxE0H
xxA7H
xxF0H
xx71H
xx72H
xx75H
xx74H
xx77H
xx97H
xx99H
xx96H
xx96H
xx96H
xx96H
xx80H
(12)
Oper
Read
Read
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Second Bus Cycle
Addr
PBA
PBA
RA
BA
A 0
A 0
X
X
X
X
X
X
X
X
X
X
WC (L,H) = Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
WD(L,H)
BC(L,H)
Data
GSRD
xxD0H
xxD0H
xxD0H
xxD0H
BSRD
xx01H
xx02H
xx03H
xx04H
WCL
WCL
BCL
PD
PD
(12)
Oper
Write
Write
Write
Write
Write
Third Bus Cycle
Addr
PA
PA
PA
X
X
WD(H,L)
BC(H,L)
WCH
WCH
Data
BCH