E28F016SA-100 Intel, E28F016SA-100 Datasheet - Page 41

• Manufacturer Part Number: E28F016SA-100
• Manufacturer: Intel

Specifications of E28F016SA-100

• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
CE# is defined as the latter of CE
1.
2.
3.
4.
5.
6.
7.
ADDRESSES (A)
NOTES:
1.
2.
3.
4.
5.
ADDRESSES (A)
CEx # (E)
OE# (G)
WE# (W)
DATA (D/Q)
RY/BY# (R)
RP# (P)
NOTE 1
NOTE 2
NOTE 4
V
PP
(V)
SEE NEW DESIGN RECOMMENDATIONS
Read timings during data program and block erase are the same as for normal read.
Refer to command definition tables for valid address and data values.
Sampled, but not 100% tested.
Data program/block erase durations are measured to valid Status Register data.
Word/byte program operations are typically performed with 1 programming pulse.
Address and data are latched on the rising edge of WE# for all command write operations.
This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office
for more information.
This address string depicts data program/block erase cycles with corresponding verification via ESRD.
This address string depicts data program/block erase cycles with corresponding verification via CSRD.
This cycle is invalid when using CSRD for verification during data program/block erase operations.
CE
RP# low transition is only to show t
V
V
POWER-DOWN
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OH
OL
PPL
IN
IH
IH
IH
IH
IH
IH
IH
PPH
IL
IL
IL
IL
IL
IL
IL
IL
X
DEEP
# is defined as the latter of CE
HIGH Z
t
ELWL
t
PHWL
t
ERASE SETUP COMMAND
DVWH
WRITE DATA-WRITE OR
t
t
AVAV
AVAV
D
IN
Figure 15. AC Waveforms for Command Write Operations
t
WLWH
t
t
WHEH
t
WHDX
WHWL
0
# or CE
ERASE CONFIRM COMMAND
& DATA (DATA-WRITE) OR
WRITE VALID ADDRESS
t
t
AVWH
AVWH
0
RHPL
# or CE
A
A
IN
IN
1
# going low or the first of CE
D
; not valid for above read and program cycles.
IN
t
VPWH
1
# going low or the first of CE
t
t
WHAX
WHAX
AUTOMATED DATA-WRITE
t
OR ERASE DELAY
WHRL
t
WHGL
t
WHQV1,2
WRITE READ EXTENDED
REGISTER COMMAND
0
# or CE
NOTE 3
0
D
# or CE
IN
1
# going high.
1
# going high.
STATUS REGISTER DATA
STATUS REGISTER DATA
READ COMPATIBLE
t
READ EXTENDED
RHPL
A=RA
D
OUT
NOTE 5
t
t
QVVL
GHWL
28F016SA
D
IN
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