CY7C68001-56LFC Cypress Semiconductor Corp, CY7C68001-56LFC Datasheet - Page 2

• Manufacturer Part Number: CY7C68001-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68001-56LFC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

4. Introduction
The EZ-USB SX2™ USB interface device is designed to work
with any external master, such as standard microprocessors,
DSPs, ASICs, and FPGAs to enable USB 2.0 support for any
peripheral design. SX2 has a built in USB transceiver and Serial
Interface Engine (SIE), along with a command decoder for
sending and receiving USB data. The controller has four
endpoints that share a 4 KB FIFO space for maximum flexibility
and throughput, and Control Endpoint 0. SX2 has three address
pins and a selectable 8- or 16- bit data bus for command and data
input or output.
Figure 4-1. Example USB System Diagram
5. Functional Overview
5.1 USB Signaling Speed
SX2 operates at two of the three rates defined in the Universal
Serial Bus Specification Revision 2.0, dated April 27, 2000:
■
■
SX2 does not support the low speed signaling rate of 1.5 Mbits/s.
5.2 Buses
SX2 features:
■
■
Document #: 38-08013 Rev. *K
Notes
1. Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0 to
2. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull up values are 2.2K–10K
Full speed, with a signaling bit rate of 12 Mbits/s
High speed, with a signaling bit rate of 480 Mbits/s.
A selectable 8- or 16-bit bidirectional data bus
An address bus for selecting the FIFO or Command Interface.
determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and double-byte
EEPROMs (24LC64, etc.) should be strapped to address 001.
Ohms.
D evice C P U
C ypress
S X2
W indows/U S B C apable H ost
U S B C onnection
U S B
R A M /R O M
C able
A pplication
E E P R O M
5.3 Boot Methods
During the power up sequence, internal logic of the SX2 checks
for the presence of an I
it boots off the EEPROM. When the presence of an EEPROM is
detected, the SX2 checks the value of first byte. If the first byte
is found to be a 0xC4, the SX2 loads the next two bytes into the
IFCONFIG and POLAR registers, respectively. If the fourth byte
is also 0xC4, the SX2 enumerates using the descriptor in the
EEPROM, then signals to the external master when enumeration
is complete through an ENUMOK interrupt (See
System”
on the external master for the descriptors. After this descriptor
information is received from the external master, the SX2
connects to the USB and enumerates.
5.3.1 EEPROM Organization
The valid sequence of bytes in the EEPROM are displayed in the
following table.
Table 5-1. Descriptor Length Set to 0x06: Default
Enumeration
Table 5-2. Descriptor Length Not Set to 0x06
Byte Index
Byte Index
0
1
2
3
4
5
6
7
8
10
11
0
1
2
3
4
5
6
7
8
9
on page 3.). If no EEPROM is detected, the SX2 relies
0xC4
IFCONFIG
POLAR
0xC4
Descriptor Length (LSB)
Descriptor Length (MSB
Descriptor[0]
Descriptor[1]
Descriptor[2]
0xC4
IFCONFIG
POLAR
0xC4
Descriptor Length (LSB):0x06
Descriptor Length (MSB): 0x00
VID (LSB)
VID (MSB)
PID (LSB)
PID (MSB)
DID (LSB)
DID (MSB)
2
C EEPROM.
Description
Description
[1,2]
If it finds an EEPROM,
CY7C68001
Page 2 of 45
“Interrupt
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