CY7C68001-56LFC Cypress Semiconductor Corp, CY7C68001-56LFC Datasheet - Page 7

• Manufacturer Part Number: CY7C68001-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68001-56LFC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

5.7.8 Command Protocol
An address of [1 0 0] on FIFOADR [2:0] selects the command
interface. The command interface is used to write to and read
from the SX2 registers and the Endpoint 0 buffer, as well as the
descriptor RAM. Command read and write transactions occur
over FD[7:0] only. Each byte written to the SX2 is either an
address or a data byte, as determined by bit7. If bit7 = 1, then
the byte is considered an address byte. If bit7 = 0, then the byte
is considered a data byte. If bit7 = 1, then bit6 determines
whether the address byte is a read request or a write request. If
bit6 = 1, then the byte is considered a read request. If bit6 = 0
then the byte is considered a write request. Bits [5:0] hold the
register address of the request. The format of the command
address byte is shown in
Table 5-4. Command Address Byte
Each Write request is followed by two or more data bytes. If
another address byte is received before both data bytes are
received, the SX2 ignores the first address and any incomplete
data transfers. The format for the data bytes is shown in
Table 5-5
Each byte is transferred using the same protocol.
Table 5-5. Command Data Byte One
Table 5-6. Command Data Byte Two
The first command data byte contains the upper nibble of data,
and the second command byte contains the lower nibble of data.
Write Request Example
Prior to writing to a register, two conditions must be met:
FIFOADR[2:0] must hold [1 0 0], and the Ready line must be
HIGH. The external master should not initiate a command if the
READY pin is not in a HIgh state.
Example: to write the byte <10110000> into the IFCONFIG
register (0x01), first send a command address byte as follows.
Table 5-7. Command Address Write Byte
Document #: 38-08013 Rev. *K
dress/Da
Address/
Note
Bit 7
5. An important note: Once the SX2 receives a Read request, the SX2 allocates the interrupt line solely for the read request. If one of the six interrupt sources described
Data#
Bit 7
Bit 7
Ad-
ta#
0
0
1
in
Interrupt System
Write#
and
Read/
Bit 6
Bit 6
Write#
Read/
X
Bit 6
X
0
Table
Bit 5
Bit 5
A5
X
X
Bit 5
0
on page 3 is asserted, the SX2 buffers that interrupt until the read request completes.
A5
5-6. Some registers take a series of bytes.
Table
Bit 4
Bit 4
A4
X
Bit 4
X
0
A4
5-4.
Bit 3
Bit 3
D3
D7
A3
Bit 3
0
A3
Bit 2
Bit 2
Bit 2
D6
D2
A2
0
A2
Bit 1
Bit 1
Bit 1
D5
A1
D1
A1
0
Bit 0
Bit 0
Bit 0
D4
A0
D0
A0
1
■
■
■
After the byte has been received the SX2 pulls the READY pin
low to inform the external master not to send any more infor-
mation. When the SX2 is ready to receive the next byte, the SX2
pulls the READY pin high again. This next byte, the upper nibble
of the data byte, is written to the SX2 as follows.
Table 5-8. Command Data Write Byte One
■
■
■
After the byte has been received the SX2 pulls the READY pin
low to inform the external master not to send any more infor-
mation. When the SX2 is ready to receive the next byte, the SX2
pulls the READY pin high again. This next byte, the lower nibble
of the data byte is written to the SX2.
Table 5-9. Command Data Write Byte Two
At this point the entire byte <10110000> is transferred to register
0x01 and the write sequence is complete.
Read Request Example
The Read cycle is simpler than the write cycle. The Read cycle
consists of a read request from the external master to the SX2.
For example, to read the contents of register 0x01, a command
address byte is written to the SX2 as follows.
Table 5-10. Command Address Read Byte
When the data is ready to be read, the SX2 asserts the INT# pin
to tell the external master that the data it requested is waiting on
FD[7:0].
dress/Da
dress/Da
Address/
The first bit signifies an address transfer.
The second bit signifies that this is a write command.
The next six bits represent the register address (000001 binary
= 0x01 hex).
The first bit signifies that this is a data transfer.
The next three are don’t care bits.
The next four bits hold the upper nibble of the transferred byte.
Data#
Ad-
Ad-
ta#
ta#
0
1
0
[5]
Write#
Read/
Don’t
Care
Don’t
Care
X
1
X
Don’t
Care
Don’t
Care
A5
0
X
X
Don’t
Care
Don’t
Care
A4
X
0
X
A3
D7
D3
0
1
0
A2
D6
D2
0
0
0
CY7C68001
A1
D1
D5
0
0
1
Page 7 of 45
A0
D4
D0
1
1
0
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