CY7C374I-66JC Cypress Semiconductor Corp, CY7C374I-66JC Datasheet

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CY7C374I-66JC

Manufacturer Part Number
CY7C374I-66JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C374I-66JC

Family Name
FLASH370i
Memory Type
Flash
# Macrocells
128
Number Of Usable Gates
3200
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
8
# I/os (max)
64
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C374I-66JC
Manufacturer:
CY
Quantity:
237
Part Number:
CY7C374I-66JC
Manufacturer:
CYP
Quantity:
200
Cypress Semiconductor Corporation
Document #: 38-03031 Rev. *A
Features
Selection Guide
Maximum Propagation Delay
Minimum Set-up, t
Maximum Clock to Output
Typical Supply Current, I
Note:
Logic Block Diagram
• 128 macrocells in eight logic blocks
• 64 I/O pins
• Five dedicated inputs including four clock pins
• In-System Reprogrammable™ (ISR™) Flash technology
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
• Pin-compatible with the CY7C373i
1. The 3.3V I/O mode timing adder, t
— JTAG interface
— f
— t
— t
— t
TQFP packages
MAX
PD
S
CO
= 5.5 ns
= 10 ns
= 6.5 ns
= 125 MHz
I/O
I/O
S
I/O
I/O
16
24
8
0
–I/O
–I/O
–I/O
–I/O
CC
15
23
31
[1]
7
[1]
, t
8 I/Os
8 I/Os
8 I/Os
8 I/Os
, t
3.3IO
CO
PD
, must be added to this specification when V
7C374i–125 7C374i–100 7C374i–83 7C7374iL–83 7C374i–66 7C374iL–66 Unit
125
5.5
6.5
10
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
4
32
C
D
A
B
UltraLogic™ 128-Macrocell Flash CPLD
MACROCELL
3901 North First Street
INPUT
125
12
6
7
36
16
36
16
36
16
36
16
Inputs
1
PIM
Functional Description
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
all members of the F
designed to bring the ease of use as well as PCI Local Bus
Specification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogic™ F
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISR
because of the superior routability of the F
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
LASH
CCIO
125
15
Inputs
Clock
8
8
= 3.3V.
370i™ family of high-density, high-speed CPLDs. Like
4
36
16
36
16
36
16
36
16
INPUT/CLOCK
MACROCELLS
San Jose
BLOCK
LOGIC
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
32
H
15
75
G
F
E
8
8
4
LASH
,
CA 95134
LASH
370i family, the CY7C374i is
8 I/Os
8 I/Os
8 I/Os
8 I/Os
125
20
10
10
370i devices, the CY7C374i
I/O
I/O
I/O
I/O
Revised April 19, 2004
56
48
40
32
–I/O
–I/O
–I/O
–I/O
LASH
EN
CY7C374i
63
55
47
39
408-943-2600
20
10
10
75
). Additionally,
370i devices,
mA
ns
ns
ns

Related parts for CY7C374I-66JC

CY7C374I-66JC Summary of contents

Page 1

... F ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. The 128 macrocells in the CY7C374i are divided between eight logic blocks. Each logic block includes 16 macrocells product term array, and an intelligent product term allocator ...

Page 2

... I I/O I/O V GND I I/O GND CLK0 I I/O I/O V ISR I/O I/O I/O I/O I/O GND I/O I/O I/O I GND CY7C374i GND I/O /SDI I/O 48 CLK / GND CCIO CLK / I I I/O ...

Page 3

... I/O I/O I/O I/O I/O GND Document #: 38-03031 Rev. *A TQFP Top View CLCC Top View CY7C374i SDI 74 V CCIO 73 I I CLK / GND CCIO CLK / I GND GND I/O /SDI 54 71 I I/O 51 ...

Page 4

... PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C374i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...

Page 5

... V = Min 0. Min 2. Max Max CCINT CY7C374i Ambient Temperature CCINT 5V ± 0.25V 5V ± 0.25V or 0°C to +70°C 3.3V ± 0.3V −40°C to +85°C 5V ± 0.5V 5V ± 0.5V or 3.3V ± 0.3V –55°C to +125°C 5V ± 0.5V Min. Typ. Max. [5] 2.4 [ ...

Page 6

... OUTPUT 236Ω (MIL INCLUDING JIG AND (b) SCOPE 2.08V (COM'L) 2.13V (MIL) Output Waveform Measurement Level V OH –0.5V –0. –0. –0.5V measured with 35-pF AC Test Load. EA CY7C374i Min. Max Max. 100 ALL INPUT PULSES 3.0V 90% 10% GND <2ns Max. EN Unit Unit ...

Page 7

... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...

Page 8

... Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Document #: 38-03031 Rev. *A [14] 7C374i–125 Min. Max. [9] 10 [9] 12 [1] 16 [9] 10 [9] 12 [1] 16 500 PDL CY7C374i 7C374i–83 7C374i–66 7C374i–100 7C374iL–83 7C374iL–66 Min. Max. Min. Max. Min 500 500 500 ...

Page 9

... OUTPUT CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: 38-03031 Rev PDL ICOL t ICS t WH CY7C374i t IH ICO ICO PDLL Page ...

Page 10

... Ordering Information Speed (MHz) Ordering Code 125 CY7C374i–125AC CY7C374i–125JC 100 CY7C374i–100AC CY7C374i–100JC CY7C374i–100AI CY7C374i–100JI 83 CY7C374i–83AC CY7C374i–83JC CY7C374i–83AI CY7C374i–83JI CY7C374i–83GMB CY7C374i–83YMB CY7C374iL–83AC CY7C374iL–83JC Document #: 38-03031 Rev Package Name ...

Page 11

... Ordering Information Speed (MHz) Ordering Code 66 CY7C374i–66AC CY7C374i–66JC CY7C374i–66AI CY7C374i–66JI CY7C374i–66GMB CY7C374i–66YMB CY7C374iL–66AC CY7C374iL–66JC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups CC1 Document #: 38-03031 Rev. *A Package Name Package Type A100 100-Pin Thin Quad Flat Pack ...

Page 12

... Package Diagrams Document #: 38-03031 Rev. *A 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 CY7C374i 51-85048-*B Page ...

Page 13

... Package Diagrams (continued) Document #: 38-03031 Rev. *A 84-Pin Grid Array (Cavity Up) G84 84-Lead Plastic Leaded Chip Carrier J83 CY7C374i 51-80015-*A 51-85006-*A Page ...

Page 14

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 84-Pin Ceramic Leaded Chip Carrier Y84 CY7C374i 51-80095-*A Page ...

Page 15

... Document History Page Document Title: CY7C374i UltraLogic™ 128-Macrocell Flash CPLD Document Number: 38-03031 REV. ECN NO. Issue Date ** 106376 07/11/01 *A 213375 See ECN Document #: 38-03031 Rev. *A Orig. of Change SZV Changed from Spec number: 38-00496 to 38-03031 FSG Added note to title page: “Use Ultra37000 For All New Designs” ...

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