CY7C374I-100JC Cypress Semiconductor Corp, CY7C374I-100JC Datasheet
CY7C374I-100JC
Specifications of CY7C374I-100JC
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CY7C374I-100JC Summary of contents
Page 1
... F often allows users to change existing logic designs while si- multaneously fixing pinout assignments. The 128 macrocells in the CY7C374i are divided between eight logic blocks. Each logic block includes 16 macrocells product term array, and an intelligent product term allocator. ...
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... GND CCIO CLK / I I I 7C374i-2 I/O I/O I/O I I/O I/O GND I SDO I/O I I/O I CLK2 I/O I I/O GND CC 45 I/O I/O CLK3 I/O I I/O I SDI I/O I/O GND I I/O I/O I/O I 7C374i–3 CY7C374i Page ...
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... CLCC Top View SDI 74 V CCIO 73 I I I CLK / GND CCIO CLK / I I I I/O 40 GND 7C374i GND I/O /SDI I/O 48 CLK / GND CLK / I 7C374i-2 CY7C374i Page ...
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... PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C374i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...
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... Output Disabled Max 0.5V CC OUT V = Max mA, CC OUT [10 MHz GND Min 0. Min 2. Max Max CCINT CY7C374i Ambient V CC Temperature V CCINT + 0.25V + 0.5V –55°C to +125°C 5V 0.5V Min. Typ. Max. [5] 2.4 [5, 6] 4.0 [5, 6] 3.6 [5] 0.5 [7] 2.0 7.0 [7] –0.5 0.8 –10 +10 –50 +50 ...
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... INCLUDING JIG AND SCOPE (b) 7C374i-5 2.08V (COM'L) 2.13V (MIL) Output Waveform Measurement Level V OH –0.5V –0. –0. –0.5V measured with 35-pF AC Test Load. EA CY7C374i Min. Max 84-Lead 84-Lead PLCC CLCC Max. 100 ALL INPUT PULSES 3.0V 90% 10% GND <2ns ( Max. ...
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... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...
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... Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Document #: 38-03031 Rev. ** [14] (continued) 7C374i–125 Min. Max. [9] 10 [9] 12 [1] 16 [9] 10 [9] 12 [1] 16 500 PDL CY7C374i 7C374i–83 7C374i–66 7C374i–100 7C374iL–83 7C374iL–66 Min. Max. Min. Max. Min 500 500 500 Max ...
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... Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: 38-03031 Rev PDL ICOL t ICS t WH CY7C374i t IH ICO ICO PDLL 7C374i-10 7C374i-11 7C374i-12 Page ...
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... Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Document #: 38-03031 Rev CY7C374i 7C374i-13 7C374i-14 7C374i-16 Page ...
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... CY7C374i–100JI 83 CY7C374i–83AC CY7C374i–83JC CY7C374i–83AI CY7C374i–83JI CY7C374i–83GMB CY7C374i–83YMB CY7C374iL–83AC CY7C374iL–83JC 66 CY7C374i–66AC CY7C374i–66JC CY7C374i–66AI CY7C374i–66JI CY7C374i–66GMB CY7C374i–66YMB CY7C374iL–66AC CY7C374iL–66JC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups ...
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... Package Diagrams Document #: 38-03031 Rev. ** 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 CY7C374i 51-85048-A Page ...
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... Package Diagrams (continued) Document #: 38-03031 Rev. ** 84-Pin Grid Array (Cavity Up) G84 84-Lead Plastic Leaded Chip Carrier J83 CY7C374i 51-80015-A 51-85006-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 84-Pin Ceramic Leaded Chip Carrier Y84 CY7C374i 51-80095-A Page ...
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... Document Title: cy7c374iUltraLogic™ 128-Macrocell Flash CPLD Document Number: 38-03031 Issue REV. ECN NO. Date ** 106376 07/11/01 Document #: 38-03031 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00496 to 38-03031 CY7C374i Page ...