CY7C1361B-100AI Cypress Semiconductor Corp, CY7C1361B-100AI Datasheet - Page 10

• Manufacturer Part Number: CY7C1361B-100AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361B-100AI

• Density: 9Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05302 Rev. *B
CY7C1363B: Pin Definitions
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
Name
1
2
3
A,
[2]
BW
B
Enable)
(3-Chip
TQFP
93,94
88
87
89
98
97
92
86
83
84
Enable)
(2-Chip
TQFP
93,94
88
87
89
98
97
86
83
84
–
(continued)
Enable)
(2-Chip
L5,G3
BGA
M4
H4
K4
E4
B2
G4
A4
F4
–
Enable)
(3-Chip
B5,A4
fBGA
B7
A7
B6
A3
B3
A6
B8
A9
B9
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
I/O
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of
CLK.
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device. ADSP is ignored
if CE
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device.
Output Enable, asynchronous input,
active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
OE is masked during the first clock of a read
cycle when emerging from a deselected
state.
Advance Input signal, sampled on the
rising edge of CLK. When asserted, it
automatically increments the address in a
burst cycle.
Address Strobe from Processor,
sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE
1
[A:B]
is deasserted HIGH.
1
is HIGH.
and BWE).
Description
2
1
1
and CE
and CE
and CE
CY7C1361B
CY7C1363B
3
3
2
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