P80C592FFA NXP Semiconductors, P80C592FFA Datasheet - Page 52

• Manufacturer Part Number: P80C592FFA
• Manufacturer: NXP Semiconductors

Specifications of P80C592FFA

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: CAN/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
13.5.19.2 Time Segment 1 (TSEG1)
This segment determines the location of the sampling
point within a bit period, which is at the end of TSEG1.
TSEG1 is programmable from 1 to 16 system clock cycles
(see Section 13.5.10).
The correct location of the sample point is essential for the
correct functioning of a transmission. The following points
must be taken into consideration:
1996 Jun 27
handbook, full pagewidth
A Start-Of-Frame (see Section 13.6.2) causes all
CAN-controllers to perform a ‘hard synchronization’
(see Section 13.5.20) on the first recessive-to-dominant
edge.
During arbitration, however, several CAN-controllers
may simultaneously transmit. Therefore it may require
twice the sum of bus-line, input comparator and the
output driver delay times until the bus is stable.
This is the propagation delay time.
8-bit microcontroller with on-chip CAN
(a) As defined by the CAN-protocol.
(b) As implemented in the P8xC592's on-chip CAN-controller.
transmit point
1 clock cycle (t
SYNC.SEG
t SYNCSEG
SCL
)
PROP.SEG
Fig.18 Bit period.
t TSEG1
nominal bit time
t (one bit period)
52
PHASE SEG1
(a)
(b)
To avoid sampling at an incorrect position, it is
necessary to include an additional synchronization
buffer on both sides of the sample point.
The main reasons for incorrect sampling are:
– Incorrect synchronization due to spikes on the
– Slight variations in the oscillator frequency of each
Time Segment 1 consists of the segment for
compensation of propagation delays and the
synchronization buffer segment directly before the
sample point (see Fig.18).
bus-line
CAN-controller in the network, which results in a
phase error.
sample point
sample point
PHASE SEG2
t TSEG2
MGA163
Product specification
P8xC592