CY7B991-2JCT Cypress Semiconductor Corp, CY7B991-2JCT Datasheet - Page 5

• Manufacturer Part Number: CY7B991-2JCT
• Manufacturer: Cypress Semiconductor Corp
• Type: Zero Delay Programmable PLL Clock Bufferr

Specifications of CY7B991-2JCT

• Number Of Elements: 1
• Supply Current: 85mA
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Output Frequency Range: 3.75 to 80MHz
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

Figure 2
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B991 or CY7B992 to operate as explained in
Matrix”
inputs can have a removable jumper to ground, or be tied LOW
through a 100Ω resistor. This enables an external tester to
change the state of these pins.
Document Number: 38-07138 Rev. *E
Note
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
(N/A)
(N/A)
(N/A)
(N/A)
1Fx
2Fx
MM
MH
HM
HH
LM
LH
ML
HL
LL
on page
shows the typical outputs with FB connected to a zero skew output.
4.
LL/HH
(N/A)
(N/A)
(N/A)
(N/A)
3Fx
4Fx
MM
MH
HM
HH
LM
LH
ML
HL
For testing purposes, any of the three level
REFInput
FBInput
DIVIDED
INVERT
– 6t
– 4t
– 3t
– 2t
– 1t
Figure 2. Typical Outputs with FB Connected to a Zero-Skew Output
+1t
+2t
+3t
+4t
+6t
0t
U
U
U
U
U
U
U
U
U
U
U
“Skew Select
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
selects inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
[4]
CY7B991
CY7B992
Page 5 of 20
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