AD6650BBC Analog Devices Inc, AD6650BBC Datasheet - Page 18

• Manufacturer Part Number: AD6650BBC
• Manufacturer: Analog Devices Inc

Specifications of AD6650BBC

• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (typ): 3.3V
• Lead Free Status / Rohs Status: Not Compliant

AD6650
INFINITE IMPULSE RESPONSE (IIR) FILTER
The IIR filter of the AD6650 is a seventh-order low-pass filter
with an infinite impulse response. This filter cannot be bypassed
and always performs a decimation of 2. As can be seen from the
Z-transform, the IIR filter has a gain of −6.02 dB to accommodate
signal peaking within the structure. It is designed to be free of
limit cycles and is unconditionally stable. The IIR filter is
described by the Z-transform and coefficients shown in the
following equation:
where:
n
n
n
n
d
d
d
d
d
d
d
d
Figure 23 shows the magnitude response of the IIR filter in a
typical GSM/EDGE case where the ADCs are sampling at
26 MHz and the CIC filter is decimating by 12 to generate a
2.16 MHz (8× symbol rate) input rate to the IIR.
Figure 24 shows the phase response of the IIR filter over the
range of ±100 kHz after a time delay during which ~13.449 input
samples of the filter have been removed. The input rate is the
same 2.16 MHz from the above GSM/EDGE configuration.
Examining the plot shows that the IIR filter is not exactly phase
linear. (Linear phase would be flat after the time delay has been
removed). It can be seen, however, that the phase response over
IIR
0
1
2
3
4
5
6
7
0
1
2
3
= 0
= 0.12895
= 0
= 0.254698
= 0
= 1.026276
= 0
= 1
= 0.046227
= 0.278961
= 0.76021
= 1.208472
( )
z
=
–100
–120
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
(
n
0
0
×
z
7
+
n
Figure 23. IIR Frequency Response
2
×
z
(
d
5
IIR RESPONSE
7
+
×
n
z
3
7
FREQUENCY (MHz)
×
+
z
d
3
5
+
×
n
1
z
5
×
+
z
d
+
3
n
×
1
z
×
3
z
+
6
d
+
1
×
n
3
z
×
)
×
z
4
2
+
n
2
Rev. A | Page 18 of 44
×
(9)
z
2
+
n
0
)
the band of interest is essentially perfect. From −100 kHz to
+100 kHz, the phase distortion is ~0.056° rms. This phase
response is several orders of magnitude below the analog LO
and analog filter phase distortions.
RAM COEFFICIENT FILTER
The final signal processing stage is a sum-of-products decimating
filter with programmable coefficients (see Figure 25). The I-RAM
and Q-RAM data memories store the most recent complex
samples from the IIR filter with 23-bit resolution. The number
of samples stored in these memories is equal to the coefficient
length (N
stores up to 48 coefficients with 20-bit resolution. On every
CLK (up to 52 MHz) cycle, one tap for I and one tap for Q are
calculated using the same coefficients. The RCF output consists
of 16-bit or 24-bit data.
RCF Decimation Register
Each RCF channel can decimate the data rate by a factor of 1 to
8. The decimation register is a 3-bit register. The RCF decimation is
stored in Address 0x18 in the form of M
to the RCF is f
RCF Decimation Phase Register
The AD6650 uses the value stored in this register to preload the
RCF counter. Therefore, instead of starting from 0, the counter
is loaded with this value, thus creating a time offset in the
output data. This data is stored in Address 0x19 as a 3-bit
number. Time delays can be achieved in even units of the RCF
input rate, which is typically ¼ of the symbol time for GSM.
Q IN
I IN
–2 × 10
–6 × 10
6 × 10
2 × 10
–0.001
0.001
taps
–4
–4
–4
–4
–100
48 × 23
48 × 20
48 × 23
Q-RAM
C-RAM
I-RAM
), up to 48 taps. The coefficient memory, CMEM,
SAMPIIR
Figure 25. Block Diagram of the RCF
IIR PHASE RESPONSE
Figure 24. IIR Phase Response
.
–50
CHANNEL BW (kHz)
28
28
0
COARSE
SCALE
RCF
− 1. The input rate
50
25
WORD
RND
24
100