WGCE5039 882560 Intel, WGCE5039 882560 Datasheet

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WGCE5039 882560

Manufacturer Part Number
WGCE5039 882560
Description
Manufacturer
Intel
Datasheet

Specifications of WGCE5039 882560

Lead Free Status / Rohs Status
Compliant
CE5039
DVB-S Digital Satellite Tuner
with RF Bypass
Data Sheet
Features
Applications
Direct conversion tuner for quadrature down
conversion from L-band to Zero IF
Symbol rate 1-45 MSps
Excellent sensitivity <-84.5 dBm at 27.5 MSps
Independent RF AGC and baseband gain control
Fifth order baseband filters with bandwidth
adjustable from 6 to 43 MHz
Fully integrated alignment-free low phase noise
local oscillator
Selectable RF Bypass
I
3.3 Volt Supply
28 pin 5x5 mm QFN Package
DVB-S Free-to-Air Satellite receiver systems
8PSK Satellite Receiver Systems
2
C compatible control
Intel Corporation
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Bypass
Output
RF Input
CE5039
Figure 1 - Basic Block Diagram
VCO
Quadrature
Loop
Filter
1
Description
The CE5039 is a fully integrated direct conversion
tuner for digital satellite receiver systems, targeted
primarily at free-to-air DVB-S receivers where high
sensitivity is a priority. The device also contains a RF
Bypass for connecting to a second receiver module.
The CE5039 is simple to use, requiring no alignment or
tuning algorithms and uses a minimum number of
external components. The device is programmable via
a I
A complete reference design (CE9541) is available
using CE6313 demodulator.
HGCE5039 882365
HGCE5039 S L9F6 882327 28 Pin QFN Tape & Reel
WGCE5039 882560
WGCE5039 S L9FW 882559 28 Pin QFN* Tape & Reel
Copyright © 2006 Intel Corporation. All rights reserved.
PLL
2
C compatible bus.
Control
Crystal
Ordering Information
I
2
C
*Pb Free Matte Tin
-10°C to +85°C
Q
I
RF AGC
28 Pin QFN Trays
28 Pin QFN* Trays
D55747-001
February 2006

Related parts for WGCE5039 882560

WGCE5039 882560 Summary of contents

Page 1

... Ordering Information HGCE5039 882365 HGCE5039 S L9F6 882327 28 Pin QFN Tape & Reel WGCE5039 882560 WGCE5039 S L9FW 882559 28 Pin QFN* Tape & Reel Description The CE5039 is a fully integrated direct conversion tuner for digital satellite receiver systems, targeted primarily at free-to-air DVB-S receivers where high sensitivity is a priority ...

Page 2

... PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 RF Control Register 2.3 Base Band Registers 2.4 Local Oscillator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 General Control Register 3.0 Applications Information 4.0 Pin Descriptions 5.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.0 Typical Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CE5039 2 Intel Corporation Data Sheet ...

Page 3

... Figure 10 - IIP2 v Gain v Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 11 - Noise Figure v Freq at 25° Figure 12 - Noise Figure v RFin v Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure Phase Noise at 25° Figure Phase Noise v Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 15 - RFin, RF Bypass Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure Bypass Gain v Temperature Figure 17 - Baseband Filter Response 26.5 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CE5039 3 Intel Corporation Data Sheet ...

Page 4

... SDA XCAP 25 XTAL 26 VccDIG 27 VccCP 28 PUMP Table 1 - Pin Names 4 Intel Corporation Data Sheet Description Q Channel baseband output Q Channel baseband output Baseband Supply I Channel baseband output I Channel baseband output Hardware power down input Clock Data General purpose switching output Crystal oscillator feedback ...

Page 5

... Figure 3 - Detailed Block Diagram CE5039 BANDWIDTH BF ADJUST FILTER FILTER 90 deg 0 deg PHASE SPLITTER LOCK DETECT Fpd 15 BIT CHARGE PROGRAMMABLE PUMP DIVIDER Fcomp I2C BUS INTERFACE REFERENCE DIVIDER 5 Intel Corporation Data Sheet VccBB QOUT QOUT DC CORRECTION DC CORRECTION IOUT IOUT VccCP PUMP PORT P0 INTERFACE ...

Page 6

... This equation makes no allowance for LNB tuning offset at low symbol rates < 10MS/s. The baseband filter uses an automatic tuning algorithm to calibrate the filter bandwidth to the programmed requirement. This removes any variation due to operating conditions and process variations. The automatic tuning CE5039 SymbolRate = FilterBand width fc × Intel Corporation Data Sheet × ...

Page 7

... This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider, which is programmable into ratios. CE5039 7 Intel Corporation Data Sheet ...

Page 8

... Register A Register Data Data ... N N N+1 A Start Device R A Register Address Data N A Start Device R A Register Address Data N 8 Intel Corporation Data Sheet 2 C bus format. The device can Register A Stop Data N+M N Stop N A Register N Stop ... Data N N interface ...

Page 9

... Local Oscillator E Local Oscillator F General X* denotes a read only test bit CE5039 Function PLF BF7 BF6 BF5 BF4 BR4 BLF* BG3 BG2 BG1 FLF CLR P0 0 Table 2 - Register Map 9 Intel Corporation Data Sheet LEN 0 BF3 BF2 BF1 BF0 BR3 BR2 BR1 BR0 BG0 ...

Page 10

... Table 4 - Register 1 14:0 ] has been programmed. Register 0 and 1 must be therefore be Type 0 R/W Test modes 0 R/W Charge pump current 0 R/W Reference divider ratio Table 5 - Register 2 . C[0] Typ 0 400 1 550 0 750 1 1000 Table 6 - Charge Pump Currents 10 Intel Corporation Data Sheet Description Description Description Units ...

Page 11

... Table 7 - PLL Reference Divider Ratios Type 0X40 R/W Test Modes Table 8 - Register 3 Type - R Test Modes 11011 R/W Test Modes 1 R/W Bypass Enable 0 R/W Not used Table 9 - Register 4 11 Intel Corporation Data Sheet Division Ratio 128 256 160 320 Description Description ...

Page 12

... Base Band Reference Division Ratio Table 11 - Register 6 Filter bandwidth (MHz) * 5.088 ( Crystal Frequency (MHz) Type - R Base Band Lock Flag 0111 R/W Base Band Gain Select 000 R/W Test Modes Table 12 - Register 7 12 Intel Corporation Data Sheet Description Description * BR[4 : 0]) − 1 Description ...

Page 13

... Local Oscillator Registers There are seven registers that control the Local Oscillator: These are used primarily for test and evaluation by Intel Corporation. Although VCO’s can be manually programmed, the user is recommended to use the default automatic settings as these provide optimum performance. ...

Page 14

... Table 17 - Register B Type 0XD0 R/W Test Modes Table 18 - Register C Type - R Test Modes (read only) 0X10 R/W Test Modes Table 19 - Register D Type - R Test Modes (read only) 0X30 R/W Test Modes Table 20 - Register E 14 Intel Corporation Data Sheet Description Description Description Description Description Description ...

Page 15

... Clear and reset logic 0 R/W Port 0 control 0 R/W Test Mode - R Test Mode (Read only) Table 21 - Register interface will remain active and can still be used to enable the 2 C interface does not operate. 15 Intel Corporation Data Sheet Description 2 C Interface and the current write ...

Page 16

... CVdd Gnd 59 6 Gnd 8 CVdd Gnd 22 13 CVdd Gnd 32 18 CVdd Gnd 34 21 Vdd Gnd 27 40 Gnd 45 Vdd Gnd 5 51 Vdd Gnd 39 54 Vdd Gnd 55 58 SDA 22 RFAGC XTALCAP XTAL VccDIG 26 RFIN 10 VccCP PUMP 28 VccFE1 8 16 Intel Corporation Data Sheet VLNBRF ...

Page 17

... Figure 4 shows a typical application using a CE6313 as a demodulator. This is available as a reference design (CE9541) from Intel Corporation. The design uses a standard two layer board. All components are mounted on the upper surface with the lower surface as a ground plane. The RF input does not require any external matching components although a coupling capacitor is required ...

Page 18

... The value of BF can now be calculated from Equation 2 and rounded to the nearest integer: Example Conditions: fxtal = 10.111 MHz, fbw = 26.5 MHz Choose 26.5 x 5.088 − 132.35 10.111 BF = 132 The actual filter bandwidth is therefore given by: 10.111 ( ) fbw x 132 5.088 CE5039 Equation 1 ⎤ − Equation 2 ⎥ 1 ⎦ fxtal is approximately 1 MHz BR MHz 18 Intel Corporation Data Sheet ...

Page 19

... VccVCO +3.3 V voltage supply for VCO's. 4 VccLO +3.3 V voltage supply for LO circuits. 5 LOTEST For Intel testing only. Must not connect. 6 RFBYPASS RF bypass output. AC couple. Matching circuitry as shown in applications diagram. Do not connect in applications where RF bypass is not required. 7 VccRF2 +3 ...

Page 20

... Logic '0' normal mode. Logic '1' - analog sections are powered down including crystal oscillator SCL I C serial clock input CE5039 Description Same as pin 15,16 20 Intel Corporation Data Sheet Schematic Vcc Vref 10k RFAGC 30k Vcc Output SLEEP CMOS Digital input SCL CMOS Digital input ...

Page 21

... MHz) 26 VccDIG +3.3 V voltage supply for digital logic. 27 VccCP +3.3 V voltage supply for varactor tuning. 28 PUMP Charge pump output. CE5039 Description SDA 21 Intel Corporation Data Sheet Schematic CMOS Digital input/output P0 CMOS Digital output Vcc XTAL 100 XCAP 0.2 mA Vcc PUMP ...

Page 22

... Min. Max. Units 3.15 3.45 V -10 +85 °C 950 2150 MHz 4.7 kΩ Intel Corporation Data Sheet Notes The voltage on any pin must not exceed 3.6 V Package ground paddle soldered to ground Mil std 883B method 3015 cat1 Notes ...

Page 23

... AGC monotonic for RFagc from Vee to Vcc μA 150 Vee <= RFagc<= Vcc -23 dBc Baseband defined, note 1 -30 dBc RF front-end defined, note 2 -26 dBc Note 3 -38 dBc Note 4 dBm At -25 dBm input, note 2 dBm At -25 dBm input, note 3 23 Intel Corporation Data Sheet Conditions ...

Page 24

... MHz offset -132 dBc/Hz 3 deg 10 kHz to 15 MHz 10 nA Vvar = 0 MHz Max specified load +1 MHz All bandwidth settings 10 ms -30 dBc 1 Vpp differential output at 43 MHz filter bandwidth Output load = 75 ohms 1 Note 9 dBm Note 10 24 Intel Corporation Data Sheet Conditions ...

Page 25

... MHz crystal μW 100 500 Note Note MHz ac coupled sinewave 2.0 Vpp ac coupled sinewave 2 MHz -148 dBc/Hz 10 MHz crystal SSB within PLL loop bandwidth 3 0.4 μA 10 Input = Vee to VccDIG +0.3 V 0.4 V Isink = 3 mA 100 kHz 25 Intel Corporation Data Sheet Conditions ...

Page 26

... Note 11: Crystal specifications vary considerably and significantly effect the choice of external oscillator capacitor values. Each application may require separate consideration for optimum performance. CE5039 Typ. Max. Units 0.7 V μ Vcc 3.6 V 1.0 V μA 10 Vin = Vee to VccDIG 26 Intel Corporation Data Sheet Conditions ...

Page 27

... Typical Performance Data CE5039 80 LO 920MHz 70 LO 1550MHz 60 LO 2150MHz -10 -20 0 0.5 1 1.5 2 AGC Voltage Figure 5 - Gain v. RFAGC at 25°C 80 +90°C 70 +25°C 60 -15° -10 -20 0 0.5 1 1.5 2 2.5 AGC Voltage Figure 6 - Gain v RFAGC v. Temperature 27 Intel Corporation Data Sheet 2 ...

Page 28

... CE5039 20 Spec 3.1Vcc 10 3.3Vcc 0 3.5Vcc -10 -20 -30 -40 -50 - Gain Setting dB Figure 7 - IIP3 v Gain at 25°C 20 Spec +90°C 10 +25°C 0 -15°C -10 -20 -30 -40 -50 - Gain Setting dB Figure 8 - IIP3 v Gain v Temperature 28 Intel Corporation Data Sheet ...

Page 29

... CE5039 -10 -20 -30 -40 - Gain Setting dB Figure 9 - IIP2 v Gain at 25° -10 -20 -30 -40 - Gain Setting dB Figure 10 - IIP2 v Gain v Temperature 29 Intel Corporation Data Sheet Spec 3.1Vcc 3.3Vcc 3.5Vcc 70 80 Spec +90°C +25°C -15° ...

Page 30

... CE5039 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5 950 1150 1350 1550 1750 Frequency (MHz) Figure 11 - Noise Figure v Freq at 25° -80 -70 -60 -50 -40 -30 RFin (dBm) Figure 12 - Noise Figure v RFin v Temperature 30 Intel Corporation Data Sheet 1950 2150 -15C 25C 90C Spec -20 -10 ...

Page 31

... Frequency offset (Hz) Figure Phase Noise at 25°C -80.0 -85.0 -90.0 -95.0 -100.0 -105.0 -110.0 -115.0 -120.0 1000 10000 100000 Frequency offset (Hz) Figure Phase Noise v Temperature 31 Intel Corporation Data Sheet 10000000 -15degC +90degC 1000000 ...

Page 32

... Frequency (MHz) Figure 15 - RFin, RF Bypass Return Loss 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -15C +25C +90C -0.5 -1.0 950 1150 1350 1550 1750 1950 Frequency (MHz) Figure Bypass Gain v Temperature 32 Intel Corporation Data Sheet 2150 2150 ...

Page 33

... CE5039 26.5MHz filter response 10 0 -10 -20 -30 -40 -50 -60 -70 -80 - Baseband frequency (MHz) Figure 17 - Baseband Filter Response 26.5 MHz 33 Intel Corporation Data Sheet +90°C +25°C -15°C 120 ...

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