WGCE5039 882560 Intel, WGCE5039 882560 Datasheet - Page 15

• Manufacturer Part Number: WGCE5039 882560
• Manufacturer: Intel

Specifications of WGCE5039 882560

• Lead Free Status / Rohs Status: Compliant

2.5
This register controls powerdown and general control functions:
The PD bit is the ‘software’ power down control. When this bit is set to 1, all the analogue blocks are powered down
with the exception of the Crystal Oscillator. The I
RF Bypass.
Setting the SLEEP input pin high also invokes ‘software’ power down with the addition of powering down the Crystal
Oscillator to produce ‘hardware’ power down. The RF Bypass will remain active if it has been previously
programmed on the I
The CLR bit re-triggers the power-on-reset function. This resets all register values to their power-on reset default
value. The CLR bit is itself cleared. Note that the chip-wide reset will reset the I
sequence used to set this bit will not be acknowledged.
The P0 bit controls the state of the output port according to Table 22.
Bit Field
General Control Register
3:0
P0
7
6
5
4
0
1
Table 22 - Output Port States
Off, high impedance
On, current sinking
2
Name
C bus. Note that in ‘hardware’ power down, the I
CLR
PD
P0
Output Port State
-
-
Default
1
0
0
0
-
Table 21 - Register F
2
Type
R/W
R/W
R/W
R/W
C interface will remain active and can still be used to enable the
Intel Corporation
R
CE5039
15
Power Down
Clear and reset logic
Port 0 control
Test Mode
Test Mode (Read only)
2
C interface does not operate.
Description
2
C Interface and the current write
Data Sheet