M29DW324DB70N6 STMicroelectronics, M29DW324DB70N6 Datasheet - Page 16

• Manufacturer Part Number: M29DW324DB70N6
• Description: Flash 32M (4Mx8 or 2Mx16)
• Manufacturer: STMicroelectronics

Specifications of M29DW324DB70N6

• Data Bus Width: 8 bit, 16 bit
• Memory Type: NOR Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Interface Type: CFI
• Access Time: 70 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 10 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-48
• Organization: 4 MB x 8
• Lead Free Status / Rohs Status: No

M29DW324DT, M29DW324DB
Fast Program Commands
There are two Fast Program commands available
to improve the programming throughput, by writing
several adjacent words or bytes in parallel. The
Quadruple Byte Program command is available for
x8 operations, while the Double Word Program
command is available for x16 operations.
Quadruple Byte Program Command. The Qua-
druple Byte Program command is used to write a
page of four adjacent Bytes in parallel. The four
bytes must differ only for addresses A0, DQ15A-1.
Five bus write cycles are necessary to issue the
Quadruple Byte Program command.
Double Word Program Command. The Double
Word Program command is used to write a page
of two adjacent words in parallel. The two words
must differ only for the address A0.
Three bus write cycles are necessary to issue the
Double Word Program command.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Programming should not be attempted when V
is not at V
After programming has started, Bus Read opera-
tions in the Bank being programmed output the
Status Register content, while Bus Read opera-
tions to the other Bank output the contents of the
memory array.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
16/49
The first bus cycle sets up the Quadruple Byte
Program Command.
The second bus cycle latches the Address and
the Data of the first byte to be written.
The third bus cycle latches the Address and the
Data of the second byte to be written.
The fourth bus cycle latches the Address and
the Data of the third byte to be written.
The fifth bus cycle latches the Address and the
Data of the fourth byte to be written and starts
the Program/Erase Controller.
The first bus cycle sets up the Double Word
Program Command.
The second bus cycle latches the Address and
the Data of the first word to be written.
The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
PPH
.
PP
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table 7, Pro-
gram, Erase Times and Program/Erase Endur-
ance Cycles.
Unlock Bypass Command.
The Unlock Bypass command is used in conjunc-
tion with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long (as with some EPROM program-
mers) considerable time saving can be made by
using these commands. Three Bus Write opera-
tions are required to issue the Unlock Bypass
command.
Once the Unlock Bypass command has been is-
sued the bank enters Unlock Bypass mode. The
Unlock Bypass Program command can then be is-
sued to program addresses within the bank, or the
Unlock Bypass Reset command can be issued to
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.
When V
the memory automatically enters the Unlock By-
pass mode and the Unlock Bypass Program com-
mand can be issued immediately.
Unlock Bypass Program Command.
The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the ad-
dress and data, and starts the Program/Erase
Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. The
operation cannot be aborted, a Bus Read opera-
tion to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.
Unlock Bypass Reset Command.
The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
Chip Erase Command.
The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are re-
quired to issue the Chip Erase Command and start
the Program/Erase Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
PP
is applied to the V
PP
/Write Protect pin