CAT24WC02J Catalyst / ON Semiconductor, CAT24WC02J Datasheet - Page 6

• Manufacturer Part Number: CAT24WC02J
• Description: EEPROM (256x8) 2k 2.5-6.0
• Manufacturer: Catalyst / ON Semiconductor

Specifications of CAT24WC02J

• Memory Size: 2 Kbit
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 2.5 V, 6 V
• Operating Temperature: 0 C to + 70 C
• Lead Free Status / Rohs Status: No

CAT24WC01/02/04/08/16
Figure 5. Slave Address Bits
*
**
*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
address. The CAT24WC01/02/04/08/16 then performs
a Read or Write operation depending on the state of the
R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC01/02/04/08/16 responds with an ac-
knowledge after receiving a START condition and its
slave address. If the device has been selected along
with a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT24WC01/02/04/08/16 is in a READ mode
it transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC01/02/04/08/16 will
continue to transmit data. If no acknowledge is sent by
the Master, the device terminates data transmission and
waits for a STOP condition.
Doc. No. 1022, Rev. N
Not Recommended for New Design,
Replace with CAT24C01
A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
a8, a9 and a10 correspond to the address of the memory array address word.
CAT24WC01/02
CAT24WC08
CAT24WC04
CAT24WC16
1
1
1
1
0
0
0
0
1
1
1
1
6
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24WC01/02/04/08/16. After receiving
another acknowledge from the Slave, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24WC01/02/04/08/16 ac-
knowledge once more and the Master generates the
STOP condition, at which time the device begins its
internal programming cycle to nonvolatile memory. While
this internal cycle is in progress, the device will not
respond to any request from the Master device.
Page Write
The CAT24WC01/02/04/08/16 writes up to 16 bytes of
data in a single write cycle, using the Page Write
operation. The Page Write operation is initiated in the
same manner as the Byte Write operation, however
instead of terminating after the initial word is transmitted,
0
0
0
0
A2
a10
A2
A2
A1
a9
a9
A1
A0
a8
Characteristics subject to change without notice
a8
a8
R/W
R/W
R/W
R/W
© Catalyst Semiconductor, Inc.