FM1808-70-S Ramtron, FM1808-70-S Datasheet - Page 4

• Manufacturer Part Number: FM1808-70-S
• Description: F-RAM 256K (32Kx8) 70ns 5V
• Manufacturer: Ramtron

Specifications of FM1808-70-S

• Memory Size: 256 KB
• Organization: 32 K x 8
• Interface: Parallel
• Access Time: 70 ns
• Operating Supply Voltage: 0 V to + 5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SOIC-28
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: No

bus. The entire memory operation occurs in a single
bus cycle. Therefore, any operation including read or
write can occur immediately following a write. Data
polling, a technique used with EEPROMs to
determine if a write is complete, is unnecessary.
Precharge Operation
The precharge operation is an internal condition that
prepares the memory for a new access. All memory
cycles consist of a memory access and a precharge.
The precharge is initiated by deasserting the /CE pin
high. It must remain high for at least the minimum
precharge time t
The user determines the beginning of this operation
since a precharge will not begin until /CE rises.
However, the device has a maximum /CE low time
specification that must be satisfied.
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle
involves a change of state. The memory architecture
is based on an array of rows and columns. Each read
or write access causes an endurance cycle for an
entire row. In the FM1808, a row is 32 bits wide.
Every 4-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring
frequently accessed data is located in different rows.
Regardless, F-RAM offers substantially higher write
Rev. 3.5
Nov. 2010
Signaling
Signaling
SRAM
FRAM
PC
.
Address
Address
Data
Data
Figure 2. Chip Enable and Memory Address Relationships
CE
CE
A1
A1
D1
Valid Strobing of /CE
Invalid Strobing of /CE
endurance than other nonvolatile memories.
rated endurance limit of 10
accesses per second to the same row for over 10
years.
F-RAM Design Considerations
When designing with F-RAM for the first time, users
of SRAM will recognize a few minor differences.
First, bytewide F-RAM memories latch each address
on the falling edge of chip enable. This allows the
address bus to change after starting the memory
access. Since every access latches the memory
address on the falling edge of /CE, users cannot
ground it as they might with SRAM.
Users who are modifying existing designs to use F-
RAM should examine the memory controller for
timing compatibility of address and control pins.
Each memory access must be qualified with a low
transition of /CE. In many cases, this is the only
change
relationships is shown in Figure 2 below. Also shown
is a common SRAM signal relationship that will not
work for the FM1808.
The reason for /CE to strobe for each address is two-
fold: it latches the new address and creates the
necessary precharge period while /CE is high.
D1
required.
A2
An example
A2
12
D2
D2
cycles will allow 3000
of the signal
Page 4 of 12
FM1808
The