HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 19

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

In applications where Phase Error terms are generated
faster than the processing rate of the Carrier Loop Filter, an
error accumulator is provided to accumulate errors until the
loop filter is ready for a new input. Phase Error terms are
generated at the rate I/Q samples are input to the Cartesian
to Polar Converter. However, the Carrier Loop Filter cannot
accept new input faster than CLK/6 since six CLK(f
clock edges are required to complete its processing cycle. If
the error accumulator is not used and the I/Q sample rate
exceeds CLK/6, error terms will be missed.
Note: The carrier Phase Error terms input to the loop filter
are only generated from the end-symbol samples when the
output of the I and D filter is selected for input to the
Cartesian-to-Polar converter.
Note: The loop filter lead gain term must be scaled
accordingly if the accumulator is used.
Carrier Loop Filter
The Carrier Loop Filter is second order lead/lag filter as
shown in Figure 14. The loop filter is similar to the Symbol
Tracking Loop Filter except for the additional terms from the
AFC Loop Filter and the Frequency Sweep Block. The
output of the Lag Accumulator is summed with the weighted
Phase Error term on the lead path to produce a frequency
control term. The Carrier Loop Filter is configured for
BOUNDARY
CONSTELLATION
MODULATION
DECISION
FIGURE 14. PHASE ERROR DETECTOR OPERATION (QPSK)
REGION
±180°
TABLE 8. BASIC PHASE ERROR DETECTOR SETTINGS
QPSK
8-PSK
TYPE
BPSK
θ
PHASE ROTATION BY 45°
CW
E
ACTUAL
POINT
X
PROJECTION OF PHASE ERROR (θ
INPUT TO CARTESIAN/POLAR CONVERTER
-90°
90°
X
X
22.5
45
Q
0
0
±180°
°
°
OFFSET
°
PHASE
(00 HEX)
(00 HEX)
°
(20 HEX)
θ
X
(10 HEX)
E
45°
I
0°
X
X
19
Q
-90°
90°
BOUNDARY
DECISION
REGION
1 (left shift 1)
2 (left shift 2)
3 (left shift 3)
0 (no shift)
FACTOR
±45°
SHIFT
X
X
MULTIPLICATION BY 4
I
BOUNDARY
E
DECISION
0°
REGION
) ABOUT 0°
(MODULO 2π)
EXPECTED
CONSTELLATION
POINT
Q
-22.5°
22.5°
PHASE ERROR
RANGE
±180
±90
±45
±22
CLK
X
θ
E
I
)
0°
HSP50210
operation by the Control Registers described in Tables 21
through 28 beginning on page 34.
The Carrier Tracking Loop is closed by using the loop filter
output to control the NCO or VCO used to down convert the
channel of interest. In basic configurations, the frequency
correction term controls the Synthesizer NCO in the
HSP50110 Digital Quadrature Tuner via the COF and
COFSYNC pins of the HSP50210’s serial interface (see
“Serial Output Interfaces” on page 23). In applications where
the carrier tracking is performed using the NCO on board the
HSP50210, the loop filter output is fed to the on-board NCO
as a frequency control.
The gain for the lead and lag paths of the Carrier Loop Filter
are set through a programmable mantissa and exponent.
The mantissa is a 4-bit value which weights the loop filter
input from 1.0 to 1.9375. The exponent defines a shift factor
that provides additional weighting from 2
the loop gain mantissa and exponent provide a gain range
between 2
Lead/Lag Gain = (1.0+M*2
where M = a 4-bit binary number from 0 to 15, and E is
a 5-bit binary value ranging from 0 to 31. For example, if
M = 0101 and E = 00110, the Gain = 1.3125*2
gain mantissa and exponent are set in the Carrier Loop Gain
Control Registers (see Tables 25 through 26 on page 36).
The Phase Error input to the Carrier Loop Filter is an 8-bit
fractional two’s complement number between ~1.0 to -1.0
(Format -2
BPSK, QPSK and 8-PSK. If minimum loop gain is used, the
Phase Error is shifted in significance by 2
loop gain, the Phase Error is passed almost unattenuated.
The output of the Carrier Loop filter is a 40-bit fractional
two’s complement number between ~1.0 and -1.0 (Format -
2
MSBs of the loop filter output represent the frequency
control word needed to adjust the down converting NCO for
phase lock. Tables 9 and 10 beginning on page 21 illustrate
the bit weighting of the Carrier Loop Filter into the NCO for
both tracking and acquisition sweep modes.
A limiter is provided on the Carrier lag accumulator output to
keep frequency tracking within a user defined range (see
Tables 23 and 24 on page 35). If the lag accumulator
exceeds either the upper or lower limit the accumulator is
loaded with the limit. For additional loop filter control, the
Carrier Loop Filter output can be frozen by asserting the
FZ_CT pin which nulls the Phase Error term into the loop
filter. Also, the lag accumulator can be initialized to a
particular value via the Microprocessor Interface as
described in Table 28 on page 37 and can be read via the
microprocessor interface as described in “Reading from the
Microprocessor Interface” on page 27.
0
. 2
-1
2
-2
2
-32
0
-3
. 2
..... 2
and
-1
2
-2
-39
~
2
1.0 as given by Equation 11.
-3
2
2
-40
-4
2
). In typical applications, the 32
-5
-4
2
)*2
-6
2
-(32 -E)
-7
). Some LSBs are zero for
-1
-32
to 2
. With maximum
-26
-32
. The loop
. Together
(EQ. 11)
July 2, 2008
FN3652.5