HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 28

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

A different read procedure is required depending on
whether the Lock Detector Accumulators, loop filter
accumulators, or the Status Register is to be read. The
read procedures are summarized in Figures 21 through 23.
The accumulators in the AGC Loop Filter, Carrier Loop
Filter and Symbol Tracking Loop can be read via the
Microprocessor Interface. Since these accumulators are
free running, their contents must be loaded into output
holding registers before they can be read. Each
accumulator has its own output holding register. The three
holding registers are updated by loading 29 (decimal) into
the Write Address Register of the Microprocessor Interface.
The output of a particular holding register is then enabled
for reading by loading its address into the Read Address
Register (see Tables 12 and 13). The holding register
addresses for the loop filter accumulators range from 0 to 4
as given in Table 13. The contents of the output holding
registers are multiplexed out a byte at a time on C7-0 by
changing A2-0 and asserting RD (see Read/Write Address
Map in Table 12).
REGISTERS
Total = 16
(4)
(4)
(1)
(2)
(2)
(2)
(1)
#
32-bit Carrier Loop Letter Lag Acc. Output
32-bit Symbol Tracking Loop Letter Lag Acc. Output
8-bit AGC Loop Letter Output
16-bit Lock Detector φe Acc. Output
16-bit Lock Detector GE Acc. Output
16-bit Lock Detector FL/FE Acc. Output
8-bit Internal Status
28
DEFINITION
HSP50210
The contents of the three accumulators in the Lock Detector
can also be read via the Microprocessor Interface. However,
the Lock Detector must be stopped before a read can be
performed. In State Machine Control Mode, the Lock
Detector is stopped by loading 24 (decimal) into the Write
Address Register. In Microprocessor Control Mode, the Lock
Detector stops after each Integration Period. To determine
when the Lock Detector has stopped and is ready for
reading, bits 7 and 6 of the Internal Status Register (SR7
and 6) must be monitored (see Table 14 on page 30). The
control sequence for reading a Lock Detector Accumulator is
shown in Figure 23. The control sequence for reading a Lock
Detector Accumulator using the LKINT signal is shown in
Figure 24.
An 8-bit Internal Status Register (SR7-0) can also be
monitored via the Microprocessor interface. The Status
Register indicates loop filter and Lock Detector status as
listed in Table 14 on page 30. The Status Register contents
are output on C7-0 by setting A2-0 to 100(binary) an
asserting RD as shown in Figure 25 on page 31. The
register contents are updated each CLK.
ADDRESS
0
1
2
3
4
TABLE 13. READ ENABLE ADDRESS MAP
Carrier Loop Filter Lag Accumulator. Enables output
of holding register containing 32 MSBs of the lag
accumulator.
Symbol Tracking Loop Filter Lag Accumulator.
Enables output of holding register containing 32
MSBs of the lag accumulator.
AGC GAIN. Enables output of holding register
containing 8 MSBs of the AGC accumulator.
Lock Detector 1. The 16 MSBs of the Lock Detector’s
Phase Error Accumulator and the 16 MSBs of the
False Lock Accumulator are enabled for output. The
accumulator contents are selected for output as
follows, A2-0 = 3 (decimal) selects MSByte of the
Phase Error Accumulator, A2-0 = 2 (decimal) selects
LSByte of the Phase Error Accumulator, A2-0 = 1
(decimal) selects MSByte of the False Lock
Accumulator, and A2-0 = 0 (decimal) selects LSByte
of the False Lock Accumulator.
Lock Detector 2. Enables the 16 MSBs of the Lock
Detector’s Gain Error Accumulator for output. The
MSByte of the accumulator is selected for output by
setting A2-0 = 1, and the LSByte is selected by A2-0
= 0.
HOLDING REGISTER ENABLE
July 2, 2008
FN3652.5