ISPLSI2128-100LM Lattice, ISPLSI2128-100LM Datasheet - Page 8

• Manufacturer Part Number: ISPLSI2128-100LM
• Description: CPLD ispLSI® 2000 Family 6K Gates 128 Macro Cells 100MHz 0.35um (EECMOS) Technology 5V
• Manufacturer: Lattice

Specifications of ISPLSI2128-100LM

• Family Name: ispLSI® 2000
• Device System Gates: 6000
• Maximum Propagation Delay Time: 13 ns
• Number Of User I/os: 128
• Number Of Logic Blocks/elements: 32
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 100 MHz
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

Power consumption in the ispLSI 2128 and 2128A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
Figure 4. Typical Device Power Consumption vs fmax
I CC can be estimated for the ispLSI 2128/A using the following equation:
I CC (mA) = 20 + (# of PTs * 0.48) + (# of nets * Max freq * 0.009)
Where:
The I CC estimate is based on typical conditions (V CC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions
and the program in the device, the actual I CC should be verified.
Power Consumption
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
300
250
200
150
100
Notes: Configuration of eight 16-bit counters
0
Typical current at 5V, 25° C
20
f
8
max (MHz)
40
used. Figure 4 shows the relationship between power
and operating speed.
Specifications ispLSI 2128/A
ispLSI 2128/A
60
80
100
0127B/2128