ADC-305-1 Murata Power Solutions Inc, ADC-305-1 Datasheet - Page 2

• Manufacturer Part Number: ADC-305-1
• Description: ADC Single 2-Step Flash 20MSPS 8-Bit Parallel 24-Pin PDIP
• Manufacturer: Murata Power Solutions Inc

Specifications of ADC-305-1

• Package: 24PDIP
• Resolution: 8 Bit
• Sampling Rate: 20000 KSPS
• Architecture: 2-Step Flash
• Number Of Analog Inputs: 1
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar

Functional Specifi cations
(Specifi cation are typical at T
+5v, f
Footnotes:
DATEL
➀ See Technical Note 4
➁ Short V
➂ Short V
PARAMETERS
Analog Inputs
Power Supply Voltage (+AVS, +DVS)
Analog Input Voltage (VIN)
Reference Input Voltage (VRT, VRB)
Digital Input Voltage (VIH, VIL)
Digital Output Voltage (VOH, VOL)
Input Voltage Range (V
Input Capacitance
Input Impedance
Input Signal Bandwidth
Ref. Resitance
Ref. Current
Ref. Voltage ➀
Offset Voltage
Self Bias I ➀ ➁ V
Self Bias II ➀ ➂ V
Input Voltage (CMOS)
Input Current (@V
Clock Pulse Width T
Output Data
Output Voltage
Output Current ➃
Output Current ➄
Output Data Delay, Td
Resolution
Maximum Sampling Rate
Minimum Sampling Rate
Aperature Delay, T
Aperature Jitter
Differential Linearity Error
Integral Linearity Error
Differential Gain Error ➅
Differential Phase Error ➅
Short V
Short V
S
(V
(V
Logic Levels (V
Logic Level (V
(@V
(A/D CLK)
Logic Level "1"
Logic Level "0"
Logic Level "1"
Logic Level "0"
®
= 20MHz sampling unless otherwise specifi ed.)
IN
IN
-2Vp-p, –1dB)
= 1.5Vdc+0.07V
IL
RB
RT
RB
RT
=0) "0"
(pin 23) to V
(pin 17) to V
(pin 23) to A GND.
(pin 17) to V
IL
IH
V
V
V
V
V
V
) "0"
IH
A
T
RT
RT
RB
RT
RB
RBS
RTS
RTS
) "1"
=+DV
PW1
PW0
RBS
RTS
RTS
to V
-V
IN
RMS
) ➀
RBS
A
S
RB
(pin 16).
(pin 16).
)"1"
(pin 22).
= +25°C, +V
)
REFERENCE INPUTS
DIGITAL Outputs
DIGITAL INPUTS
PERFORMANCE
+1.96
+2.25
Min.
+1.8
+0.6
–1.1
+3.7
230
–10
4.5
+4
25
25
20
RT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
8
–0.5
–0.5
–0.5
–0.5
–0.5
➃ OE=OV, V
➄ OE=+DV
➅ NTSC 40IRE mode ramp, 14.3MHz
MIN
= +2.5V, V
V
sampling
OL
3-State TTL compatible
+0.5 to +2.5
=+0.4V
8-bit Binary Parallel
Typ.
+0.64
+2.09
+2.39
®
12.5
±0.3
+0.5
300
–35
+15
6.6
0.5
RB
11
18
18
30
+AVS +0.5
+AVS +0.5
+DVS +0.5
+DVS +0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
1
S
OH
, V
• 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: [phone] • www.datel.com • e-mail: [e-mail]
MAX
= +0.5V, +AV
+7
=+DV
OH
=+DV
Max.
S
+0.68
+2.21
+2.53
–0.5V,
+2.8
±0.5
+1.3
450
–60
+45
V
8.7
0.5
+1
—
—
—
—
—
—
—
—
—
16
16
30
—
—
—
—
—
—
S
5
5
RT
, V
S
OL
= +DV
UNITS
Volts
Volts
Volts
Volts
Volts
=0V
Units
Volts
MHz
Volts
Volts
Volts
Volts
Volts
Volts
Volts
MHz
MHz
LSB
LSB
deg
kΩ
mA
mV
mV
mA
mA
pF
μA
μA
μA
μA
Bit
S
ns
ns
ns
ns
ps
Ω
%
=
Technical Notes
1. The ADC-305 has separate +AVS and +DVS pins. It is recommended that both +AVS
2. Bypass all power lines to ground with a 0.1μF ceramic chip capacitor in parallel with a 47μF
3. Even though the analog input capacitance is a low 15pF, it is recommended that high
4. The input voltage range is determined by voltages applied to VRB (Reference Bottom) and
Self Bias Mode
a. Tie VRB to VRBS, and tie VRT to VRTS respectively. The analog input range in this case is
b.
External Reference Mode
5. Logic inputs are CMOS compatible. Normally a series 74HC is used as a driver. It is
6. The start convert (A/D CLK) pulse can be a 50% duty cycle clock. Both TPW1 and TPW0 are
7. The digital data outputs are 3-state and TTL compatible. To enable the 3-state
8. Maximum 30ns (18ns typical) after the rising edge of the Nth conversion pulse, the
9. The 20MHz sampling rate is guaranteed. It is not recommended to use this device
POWER REQUIREMENTS
Power Supply (+AV
Power Supply Current
Power Dissipation
Operating Temp. Range
Storage Temp. Range
Package Type
Weight
and +DVS be powered from a single supply since a time lag between start up of separate
supplies could induce latch up. Other external logic circuits must be powered from a separate
digital supply. +DVS (pins 11 and 13) and +AVs (pins 14, 15 and 18) should be tied together
externally. DGND (pins 2 and 24) and AGND (pins 20 and 21) should also be tied together
externally. Power supply grounds must be connected at one point to the ground plane directly
beneath the device. Digital returns should not fl ow through analog grounds.
electrolytic capacitor. Locate the bypass capacitor as close to the unit as possible.
frequency input be provided via a high speed buffer amplifi er. A parasitic oscillation may be
generated when a high speed amplifi er is used. A 75 ohm resister inserted between the output
of an amplifi er and the analog input of the ADC-305 will improve the situation. A resistor larger
than 100 ohms may degrade linearity.
VRT (Reference Top). Keep to the following equations:
The analog input range is normally 2Vp-p.
+0.64V to +2.73V nominal.
Tie VRB to AGND, and tie VRT to VRTS respectively. The analog input voltage range is 0 to
+2.39V in this case. These values may differ from one device to another. Voltage changes on
the +5V supply have a direct infl uence on the performance of the device. The use of external
references is recommended for applications sensitive to gain error.
Tie VRB to AGND, and apply +2V to VRT to use at 0 to +2V input voltage range. The reference
resistance between VRB and VRT is about 300 ohms. It is important to make the output
impedance of the reference source small enough while, at the same time, keeping suffi cient
drive capacity. Insert a 0.1μF bypass ceramic chip capacitor between VRT and GND to
minimize the effect of the 20MHz clock running nearby. See Figure 5.
recommended to pull up to +5V if the device is driven with TTL.
25ns minimum. A slightly longer TPW1 will improve linearity of the system for higher frequency
input signals.
outputs, connect the OUTPUT ENABLE (pin 1) to GND. To disable, connect it to
+5V. It is recommended that the data outputs be latched and buffered through
output registers.
result of the (N-3) conversion can be obtained. Data is stored fi rmly in an output
register, such as an 74LS574, using the rising edge of a start convert pulse as a
trigger. The (N–4) data is stored in this case. See the timing diagrams, Figure 2
and 4.
at sampling rates slower than 500kHz because the droop characteristics of the
internal sample and holds will then exceed the limit required to maintain the
specifi ed accuracy of the device.
I A GND - D GND I
0V≤VRB≤VRT≤2.8V
1.8V≤VRT–VRB≤2.8V
8-Bit, 20MHz CMOS A/D Converters
S
, +DV
ADC-305-1
ADC-305-3
ADC-305-1
ADC-305-3
S
)
Physical/Environmental
30 Mar 2011 MDA_ADC-305.B02 Page 2 of 6
+4.75
Min.
—
—
—
24-pin Plastic SOP
24-pin Plastic DIP
Typ.
+5.0
–55 to +150°C
12
60
–40 to +85°C
—
2.0 grams
0.3 grams
ADC-305
Max.
+5.25
100
17
85
Units
Volts
mW
mV
mA