CY7C1347F-133AI Cypress Semiconductor Corp, CY7C1347F-133AI Datasheet - Page 6

• Manufacturer Part Number: CY7C1347F-133AI
• Description: SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347F-133AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4.5 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 1
• Number Of Words: 128K

Document #: 38-05213 Rev. *D
Interleaved Burst Sequence
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
Notes:
A
00
01
10
11
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
[1:0]
Address
(BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW) .
First
Parameter
A
, BW
Next Cycle
B
, BW
[2, 3, 4, 5, 6]
A
01
00
11
10
C
, BW
[1:0]
Address
Second
D
), BWE, GW = H.
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
External
External
External
External
External
A
10
11
00
01
Current
Current
Current
Current
Used
None
None
None
None
None
None
Add.
Next
Next
Next
Next
Next
Next
[1:0]
Address
Third
Description
CE
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
1
A
11
10
01
00
[1:0]
Address
CE
Fourth
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
L
2
A
, BW
CE
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
B
3
, BW
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
C
ZZ
, BW
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Linear Burst Sequence
A
00
01
10
11
[1:0]
Test Conditions
D
Address
DD
DD
ADSP ADSC ADV WRITE
) and BWE = L or GW = L. WRITE = H when all Byte write enable signals
First
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
L
L
L
L
− 0.2V
− 0.2V
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
A
01
10
11
00
[1:0]
Address
Second
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
[A:D]
L
L
L
L
L
L
. Writes may occur only on subsequent clocks
X
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
2t
Min.
CYC
0
A
10
11
00
01
[1:0]
Address
Third
OE
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
CY7C1347F
2t
2t
Max.
40
CLK
CYC
CYC
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
A
11
00
01
10
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[1:0]
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
Address
Fourth
DQ
Unit
Q
D
Q
Q
Q
Q
Q
mA
D
D
ns
ns
ns
ns