MT9044AL Zarlink, MT9044AL Datasheet - Page 7

• Manufacturer Part Number: MT9044AL
• Description: Framer E1/OC3/T1 5V 44-Pin MQFP
• Manufacturer: Zarlink

Specifications of MT9044AL

• Package: 44MQFP
• Maximum Data Rate: 2.048 Mbps
• Number Of Transceivers: 1
• Standard Framing Format: E1|OC3|T1
• Maximum Supply Current: 90 mA
• Minimum Single Supply Voltage: 4.5 V
• Maximum Single Supply Voltage: 5.5 V

Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or
SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.
During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary
reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL will
lead to unacceptable phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the
signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is
input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.
During a switch, from one reference to the other, the State Machine first changes the mode of the device from
Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an
accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the
current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the
Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as
the previous reference signal would have been if the reference switch had not taken place. The State Machine then
returns the device to Normal Mode.
PRI or SEC
Select Mux
Reference
from
Programmable
Delay Circuit
FS2
0
0
1
1
Table 1 - Input Frequency Selection
Figure 3 - TIE Corrector Circuit
FS1
0
1
0
1
Zarlink Semiconductor Inc.
State Machine
TIE Corrector
MT9044
Enable
Control
TCLR
from
Circuit
7
Resets Delay
Input Frequency
1.544 MHz
2.048 MHz
Delay Value
Reserved
8 kHz
Control Signal
Select MUX
Signal from
Frequency
Compare
Feedback
Circuit
Reference
to DPLL
Virtual
Data Sheet