MT9044AL Zarlink, MT9044AL Datasheet - Page 8

• Manufacturer Part Number: MT9044AL
• Description: Framer E1/OC3/T1 5V 44-Pin MQFP
• Manufacturer: Zarlink

Specifications of MT9044AL

• Package: 44MQFP
• Maximum Data Rate: 2.048 Mbps
• Number Of Transceivers: 1
• Standard Framing Format: E1|OC3|T1
• Maximum Supply Current: 90 mA
• Minimum Single Supply Voltage: 4.5 V
• Maximum Single Supply Voltage: 5.5 V

The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,
no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change
at the input of the DPLL, or at the output of the DPLL.
Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual
reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.
This phase error is a function of the difference in phase between the two input reference signals during reference
rearrangements. Each time a reference switch is made, the delay between input signal and output signal will
change. The value of this delay is the accumulation of the error measured during each reference switch.
The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. A
minimum reset pulse width is 300 ns. This results in a phase alignment between the input reference signal and the
output signal as shown in Figure 20. The speed of the phase alignment correction is limited to 5 ns per 125 us, and
convergence is in the direction of least phase travel.
The state diagrams of Figure 7 and 8 indicate the state changes that activate the TIE Corrector Circuit.
Digital Phase Lock Loop (DPLL)
As shown in Figure 4, the DPLL of the MT9044 consists of a Phase Detector, Limiter, Loop Filter, Digitally
Controlled Oscillator, and a Control Circuit.
Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the
feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the
proper feedback signal to be externally selected (e.g., 8 kHz, 1.544 MHz or 2.048 MHz).
Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 5 ns per 125 us. This is well within the maximum
phase slope of 7.6 ns per 125 us or 81 ns per 1.326 ms specified by AT&T TR62411, and Bellcore GR-1244-
CORE.
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all three
reference frequency selections (8 kHz, 1.544 MHz or 2.048 MHz). This filter ensures that the jitter transfer
requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT9044.
Virtual Reference from
TIE Corrector
Feedback Signal from
Frequency Select MUX
Detector
Phase
Figure 4 - DPLL Block Diagram
Limiter
Zarlink Semiconductor Inc.
MT9044
State Select from
Input Impairment
State Select from
8
State Machine
Loop Filter
Monitor
Controlled
Oscillator
Digitally
Control
Circuit
DPLL Reference to
Output Interface Circuit
Data Sheet