XC2C32A-6CP56C Xilinx Inc, XC2C32A-6CP56C Datasheet

XC2C32A-6CP56C

Manufacturer Part Number

XC2C32A-6CP56C

Description

CPLD CoolRunner™-II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA

Manufacturer

Xilinx Inc

Datasheet

1.XC2C32A-6QFG32C.pdf (14 pages)

Specifications of XC2C32A-6CP56C

Package

56CSBGA

Family Name

CoolRunnerÂ-II

Device System Gates

750

Number Of Macro Cells

Maximum Propagation Delay Time

6 ns

Number Of User I/os

Number Of Logic Blocks/elements

Typical Operating Supply Voltage

1.8 V

Maximum Operating Frequency

200 MHz

In System Programmability

Yes

Number Of Product Terms Per Macro

Operating Temperature

0 to 70 Â°C

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DS310 (v2.1) November 6, 2008

Features

•

Refer to the CoolRunner™-II family data sheet for the archi-

tecture description.

DS310 (v2.1) November 6, 2008

Product Specification

Optimized for 1.8V systems

Industry’s best 0.18 micron CMOS CPLD

Available in multiple package options

Advanced system features

As fast as 3.8 ns pin-to-pin logic delays

As low as 12 μA quiescent current

Optimized architecture for effective logic synthesis

Multi-voltage I/O operation: 1.5V through 3.3V

32-land QFN with 21 user I/Os

44-pin VQFP with 33 user I/Os

56-ball CP BGA with 33 user I/Os

Pb-free available for all packages

Fastest in system programming

IEEE1149.1 JTAG Boundary Scan Test

Optional Schmitt-trigger input (per pin)

Two separate I/O banks

RealDigital 100% CMOS product term generation

Flexible clocking modes

Optional DualEDGE triggered registers

Global signal options with macrocell control

Efficient control term clocks, output enables and

set/resets for each macrocell and shared across

function blocks

Advanced design security

Open-drain output option for Wired-OR and LED

drive

Optional configurable grounds on unused I/Os

Optional bus-hold, 3-state, or weak pullup on

selected I/O pins

Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

PLA architecture

Hot pluggable

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

1.8V ISP using IEEE 1532 (JTAG) interface

Multiple global clocks with phase selection per

macrocell

Multiple global output enables

Global set/reset

Superior pinout retention

100% product term routability across function

block

www.xilinx.com

XC2C32A CoolRunner-II CPLD

Product Specification

Description

The CoolRunner™-II 32-macrocell device is designed for

both high performance and low power applications. This

lends power savings to high-end communication equipment

and high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved.

This device consists of two Function Blocks interconnected

by a low power Advanced Interconnect Matrix (AIM). The

AIM feeds 40 true and complement inputs to each Function

Block. The Function Blocks consist of a 40 by 56 P-term

PLA and 16 macrocells which contain numerous configura-

tion bits that allow for combinational or registered modes of

operation.

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain, and programmable grounds. A Schmitt trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers can be

configured as "direct input" registers to store signals directly

from input pins.

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as a

synchronous clock source. Macrocell registers can be indi-

vidually configured to power up to the zero or one state. A

global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asynchro-

nous set/reset, and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

The CoolRunner-II 32-macrocell CPLD is I/O compatible

with standard LVTTL and LVCMOS18, LVCMOS25, and

LVCMOS33 (see

patible with the use of Schmitt-trigger inputs.

Another feature that eases voltage translation is I/O bank-

ing. Two I/O banks are available on the CoolRunner-II 32A

macrocell device that permit easy interfacing to 3.3V, 2.5V,

1.8V, and 1.5V devices.

Table

1). This device is also 1.5V I/O com-

Related parts for XC2C32A-6CP56C

XC2C32A-6CP56C Summary of contents

Page 1

... Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS310 (v2.1) November 6, 2008 Product Specification 0 XC2C32A CoolRunner-II CPLD Product Specification 0 0 Description The CoolRunner™ ...

Page 2

... LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica- tions. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C32A IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 ...

Page 3

... CCIO V = 1.9V 3.6V CC CCIO MHz MHz MHz MHz MHz 3.9V IN CCIO 3.9V IN CCIO www.xilinx.com XC2C32A CoolRunner-II CPLD Value Units –0.5 to 2.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –65 to +150 °C +150 °C Min Max Units 1.7 1 ...

Page 4

... XC2C32A CoolRunner-II CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL LVCMOS 2.5V DC Voltage Specifications Symbol Parameter ...

Page 5

... F EXT1 SU1 CO 4. Typical configuration current during T DS310 (v2.1) November 6, 2008 Product Specification Test Conditions Parameter OR array . μ is 500 A. CONFIG www.xilinx.com XC2C32A CoolRunner-II CPLD Min. Max. 1.4 3 CCIO CCIO 0 0 CCIO CCIO -4 -6 Min. Max. ...

Page 6

... XC2C32A CoolRunner-II CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Direct register input delay DIN T Global Clock buffer delay GCK T Global set/reset buffer delay GSR T Global 3-state buffer delay GTS T Output buffer delay OUT T Output buffer enable/disable delay ...

Page 7

... Number of Outputs Switching Figure 2: Derating Curve for T DS310 (v2.1) November 6, 2008 Product Specification (1) Min Test Circuit DS091_02_112002 PD www.xilinx.com XC2C32A CoolRunner-II CPLD -4 -6 Max. Min. Max. 0.5 - 0.6 3.0 - 4.0 0.6 - 0.7 4.0 - 5.0 0.5 - 0.6 3.0 - 4.0 1.0 - 1.2 4 ...

Page 8

... Function Block Macrocell 1(GTS1) 4 1(GTS0) 5 1(GTS3) 6 1(GTS2) 7 1(GSR 2(GCK0) 5 2(GCK1) 6 2(GCK2 3.3V 2.5V 1.5V .5 1.0 1.5 2.0 VO (Output Volts) Figure 4: Typical I/V Curve for XC2C32A (1) QFG32 PC44 www.xilinx.com Iol 2.5 3.0 3.5 XC32_VoIo_all_0403 VQ44 CP56 I/O Bank 38 F1 Bank Bank 2 36 ...

Page 9

... This is an obsolete package type. It remains here for legacy support only. 2. GTS = global output enable, GSR = global set reset, GCK = global clock. 3. GTS, GSR, and GCK pins can also be used for general purpose I/O. XC2C32A Global, JTAG, Power/Ground, and No Connect Pins Pin Type TCK TDI TDO ...

Page 10

... XC2C32A CoolRunner-II CPLD Ordering Information Pin/Ball Part Number Spacing (°C/Watt) XC2C32A-4QFG32C 0.5mm XC2C32A-6QFG32C 0.5mm XC2C32A-4VQ44C 0.8mm XC2C32A-6VQ44C 0.8mm XC2C32A-4CP56C 0.5mm XC2C32A-6CP56C 0.5mm XC2C32A-4VQG44C 0.8mm XC2C32A-6VQG44C 0.8mm XC2C32A-4CPG56C 0.5mm XC2C32A-6CPG56C 0.5mm XC2C32A-6QFG32I 0.5mm XC2C32A-6VQ44I 0.8mm XC2C32A-6CP56I 0.5mm XC2C32A-6VQG44I 0.8mm XC2C32A-6CPG56I 0.5mm Notes Commercial (TA = 0° ...

Page 11

... Vcc CCIO1 I/O 19 I/O TDI TMS 18 I/O TCK 17 I/O (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset I/O (2) I/O I/O GND I/O I/O V CCIO1 I/O TDI TMS TCK www.xilinx.com XC2C32A CoolRunner-II CPLD VQ44 I I/O 6 Top View 28 I CCIO2 GND 9 25 ...

Page 12

... XC2C32A CoolRunner-II CPLD K I/O J I/O H I/O G I/O F I/O E I/O D I/O C I/O B I/O A I/O (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS ...

Page 13

... Device Packages Revision , t , and t TOGGLE SLEW25 SLEW33 , T IN25 specification for 2.5V and 1.8V LVCMOS. Change for LVCMOS18; removed note for xcn07022.pdf www.xilinx.com XC2C32A CoolRunner-II CPLD . CCSB , T , and T . OUT25 IN33 OUT33 GCK, GSR, and GTS pins can also for -4 speed OEM for LVCMOS33 ...

Page 14

... XC2C32A CoolRunner-II CPLD 14 www.xilinx.com R DS310 (v2.1) November 6, 2008 Product Specification ...

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