XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet
XC2C32
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XC2C32 Summary of contents
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... Advanced design security - Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pullup on select I/O pins - Optional configurable grounds on unused I/Os Table 1: CoolRunner-II CPLD Family Parameters XC2C32A Macrocells 32 Max I (ns) 3 (ns) 1.9 SU ...
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... The ultra tiny packages permit maximum functional capacity in the smallest possible area. The CMOS technology used in CoolRunner-II CPLDs generates minimal heat, allowing the use of tiny packages during high-speed operation. Table 3: CoolRunner-II CPLD Family Packages and I/O Count XC2C32 XC2C32A (1) QFG32 21 PC44 33 33 ...
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... FBs and connected with the ability to utilize a very high percentage of device resources. Design changes are easily and automatically managed by the soft- ware, which exploits the 100% routability of the Program- mable Logic Array within each FB. This extremely robust DS090 (v2.5) June 28, 2005 Product Specification XC2C32A XC2C64 XC2C64A ...
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CoolRunner-II CPLD Family trol path. The BSC and ISP block has the JTAG controller and In-System Programming Circuits. MC1 I/O Pin MC2 I/O Pin 16 MC16 I/O Pin 16 JTAG BSC and ISP Function Block The CoolRunner-II CPLD Function Blocks ...
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R Macrocell The CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic creation. Users can develop sum of product (SOP) logic expressions that comprise inputs and span 56 product terms within a single function block. The ...
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CoolRunner-II CPLD Family software. The AIM minimizes both propagation delay and power as it makes attachments to the various FBs. I/O Block I/O blocks are primarily transceivers. However, each I/O is either automatically compliant with standard voltage ranges or can ...
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... CPLDs are widely used as voltage interface translators. To that end, the output pins are grouped in large banks. The XC2C32 and XC2C64 devices are not banked, but the new XC2C32A and XC2C64A devices have two banks. The medium parts (128 and 256 macrocell) support two output banks ...
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CoolRunner-II CPLD Family Latch Latch Figure 6: DataGATE Architecture (output drivers not shown) Global Signals Global signals, clocks (GCK), sets/resets (GSR) and output enables (GTS), are designed to strongly resemble each other. This approach enables design software to make the ...
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R CoolCLOCK In addition to the DualEDGE flip-flop, additional power sav- ings can be had by combining the clock division circuitry with the DualEDGE circuitry. This capability is called Cool- CLOCK and is designed to reduce clocking power within the ...
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CoolRunner-II CPLD Family Design Security Designs can be secured during programming to prevent either accidental overwriting or pattern theft via readback. Four independent levels of security are provided on-chip, eliminating any electrical or visual detection of configuration patterns. These security ...
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R Programming The programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester simple microprocessor interface that emulates the JTAG instruction ...
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... CCIO 1.5V operation. Two V rails are supported on the CCIO XC2C32A, XC2C64A, 128 and 256 macrocell parts where outputs on each rail can independently range from 3.3V down to 1.5V operation. Four V CCIO the 384 and 512 macrocell parts. Any of the V assume any one of the V values of 1 ...
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... Microcontroller Interface) http://direct.xilinx.com/bvdocs/appnotes/xapp394.pdf (Interfacing with Mobile SDRAM) http://direct.xilinx.com/bvdocs/appnotes/xapp399.pdf (Assigning CoolRunner-II VREF Pins) CoolRunner-II Data Sheets http://direct.xilinx.com/bvdocs/publications/ds090.pdf (CoolRunner-II Family Datasheet) http://direct.xilinx.com/bvdocs/publications/ds091.pdf (XC2C32 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds092.pdf (XC2C64 Datasheet) www.xilinx.com CoolRunner-II CPLD Family Min. Max. –0.5 2.0 –0.5 4.0 – ...
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... Update Hewlett-Packard to Agilent, OFR to OTF, and other revisions 01/26/04 1.8 Incorporate links to Data Sheets, Application Notes, and Device Packages 02/26/04 1.9 Change to Power-Up Characteristics, page 11. Change T I/O compatibility information. Added T 05/21/04 2.0 Add XC2C32A and XC2C64A devices. 07/30/04 2.1 Pb-free documentation. Changes to T 01/10/05 2.2 Added information about programming options, page 11. 03/07/05 2.3 Changes to Table 1, T Modifications to Table 5, IOSTANDARDs ...