P80C592FFA/00,518 NXP Semiconductors, P80C592FFA/00,518 Datasheet - Page 18

• Manufacturer Part Number: P80C592FFA/00,518
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,518

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Philips Semiconductors
10 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consists of an 8-input analog
multiplexer and an ADC with 10-bit resolution. The analog
reference voltage and analog power supplies are
connected via separate input pins. The conversion takes
50 machine cycles i.e. 37.5 s at 16 MHz oscillator
frequency. The input voltage swing is from 0 V to AV
The ADC is controlled using the ADCON control register.
Register bits ADCON.0 to ADCON.2 select the input
channels of the analog multiplexer (see Fig.10).
The completion of the 10-bit analog-to-digital conversion is
flagged by ADCI in the ADCON register and the result is
stored in the SFR ADCH (upper 8-bits) and the 2 lower bits
(ADC.1 and ADC.0) in register ADCON.
An analog-to-digital conversion in progress is unaffected
by an external or software ADC start. The result of a
completed conversion remains unchanged provided
ADCI = HIGH. While ADCI or ADCS are HIGH, a new ADC
START will be blocked and consequently lost. An
analog-to-digital conversion already in progress is aborted
when the Idle or Power-down mode is entered.
1996 Jun 27
handbook, full pagewidth
8-bit microcontroller with on-chip CAN
N
R
N
U
T
E
A
L
B
S
I
Fig.9 Functional diagram of Pulse Width Modulated outputs.
f clk
1/2
PRESCALER
PWMP
DD
.
8-BIT COMPARATOR
8-BIT COMPARATOR
8-BIT COUNTER
18
The result of a completed conversion (ADCI = HIGH)
remains unaffected during the Idle mode.
The LOW-to-HIGH transition of STADC is recognized at
the end of a machine cycle and the conversion
commences at the beginning of the next cycle. When a
conversion is initiated by software, the conversion starts at
the beginning of the machine cycle following the
instruction that sets ADCS.
The next two machine cycles are used to initiate the
converter. At the end of this first cycle, the ADCS status
flag is set to HIGH while the conversion is in progress.
Sampling of the analog input commences at the end of the
second cycle.
During the next eight machine cycles, the voltage at the
previously selected pin of Port 5 is sampled and this input
voltage should be stable in order to obtain a useful sample.
In any case, the input voltage slew rate must be less than
10 V/ms (5 V conversion range) in order to prevent an
undefined result. The conversion takes four machine
cycles per bit.
PWM0
PWM1
OUTPUT
OUTPUT
BUFFER
BUFFER
MGA154
PWM0
PWM1
Product specification
P8xC592