P80C592FFA/00,518 NXP Semiconductors, P80C592FFA/00,518 Datasheet - Page 43

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P80C592FFA/00,518

Manufacturer Part Number
P80C592FFA/00,518
Description
IC 80C51 MCU 8BIT ROMLESS 68PLCC
Manufacturer
NXP Semiconductors
Series
80Cr
Datasheet

Specifications of P80C592FFA/00,518

Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-LCC (J-Lead)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P80C592FFA/00,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
13.5.10 B
The contents of Bus Timing Register 1 defines the length
of the bit period, the location of the sample point and the
number of samples to be taken at each sample point.
Table 47 Bus Timing Register 1 (address 7)
Table 48 Description of the BTR1 bits
1996 Jun 27
BIT SYMBOL
7
6
5
4
3
2
1
0
8-bit microcontroller with on-chip CAN
SAM
SAM
TSEG2.2 Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2).
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0
7
US
T
IMING
TSEG2.2
Sampling. If the bit SAM is:
TSEG1 determines the number of clock cycles per bit period and the location of the sample point
TSEG2 determines the number of clock cycles per bit period and the location of the sample point:
t
t
TSEG2
TSEG1
HIGH (3 samples), then three samples are taken. This is recommended for slow/medium speed
buses (SAE class A and B) where filtering of spikes on the bus-line is beneficial
(see Section 13.5.19.6)
LOW (1 sample), the bus is sampled once.
This is recommended for high speed buses (SAE class C).
R
6
EGISTER
=
=
t
t
SCL
SCL
1(BTR1)
TSEG2.1
4TSEG2.2
8TSEG1.3
5
+
+
2TSEG2.1
TSEG2.0
4TSEG1.2
4
43
+
+
TSEG2.0
2TSEG1.1
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).For further information
on bus timing, see Sections 13.5.9 and 13.5.18.
FUNCTION
TSEG1.3
3
+
+
1
TSEG1.0
.
TSEG1.2
2
+
1
.
TSEG1.1
1
Product specification
P8xC592
TSEG1.0
0

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