SI3018-F-GSR Silicon Laboratories Inc, SI3018-F-GSR Datasheet - Page 60

• Manufacturer Part Number: SI3018-F-GSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3018-F-GSR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Register 2. Control 2
Reset settings = 0000_0011
Bit
7
6
5
4
3
2
1
0
Name
Type
Bit
Reserved Read returns zero.
Reserved Read returns zero.
WDTEN
Name
INTE
INTP
HBE
RXE
RDI
INTE
R/W
D7
Interrupt Pin Enable.
0 = The AOUT/INT pin functions as an analog output for call progress monitoring purposes.
1 = The AOUT/INT pin functions as a hardware interrupt pin.
Interrupt Polarity Select.
0 = The AOUT/INT pin, when used in hardware interrupt mode, is active low.
1 = The AOUT/INT pin, when used in hardware interrupt mode, is active high.
Watchdog Timer Enable.
0 = Watchdog timer disabled.
1 = Watchdog timer enabled. When set, this bit can be cleared only by a hardware reset. The
watchdog timer monitors register access. If no register access occurs within a 4 s window, the
DAA is put into an on-hook state. A read or write of a DAA register restarts the watchdog timer
counter. If the watchdog timer times out, the OH bit is cleared, placing the DAA into an
on-hook state. Setting the OH bit places the DAA back into an off-hook state.
Ring Detect Interrupt Mode.
This bit operates in conjunction with the RDTM and RDTI bits. This bit selects whether one or
two interrupts are generated for every ring burst.
0 = An interrupt is generated at the beginning of every ring burst.
1 = An interrupt is generated at the beginning and end of every ring burst. The interrupt at the
beginning of the ring burst must be serviced (by writing 0 to the RDTI bit) before the end of the
ring burst in order for both interrupts to occur.
Hybrid Enable.
0 = Disconnects hybrid in transmit path.
1 = Connects hybrid in transmit path.
Receive Enable.
0 = Receive path disabled.
1 = Enables receive path.
INTP
R/W
D6
D5
Rev. 1.31
WDTEN
R/W
D4
Function
D3
Si3050 + Si3018/19
R/W
RDI
D2
HBE
R/W
D1
RXE
R/W
D0
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