LTC4271IUF#PBF Linear Technology, LTC4271IUF#PBF Datasheet - Page 26

• Manufacturer Part Number: LTC4271IUF#PBF
• Manufacturer: Linear Technology

Specifications of LTC4271IUF#PBF

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 24
• Mounting: Surface Mount
• Package Type: QFN EP
• Case Length: 4mm
• Screening Level: Industrial
• Lead Free Status / Rohs Status: Compliant

LTC4270/LTC4271
APPLICATIONS INFORMATION
For simple devices such as small PoE switches, the isola-
tion requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
standard I
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to
protective ground for some other reason, the Power over
Ethernet subsystem must be electrically isolated from the
rest of the system.
The LTC4270/LTC4271 chipset simplifies PSE isolation by
allowing the LTC4271 chip to reside on the non-isolated
side. There it can receive power from the main logic sup-
ply and connect directly to the I
between the LTC4271 and LTC4270 is implemented using
a proprietary transformer-based communication protocol.
Additional details are provided in the Serial Bus Isolation
section of this data sheet.
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4270/LTC4271 requires two supply voltages to
operate. V
V
–57V for Type 1 PSEs, –50V to –57V for Type 2 PSEs,
or –54.75V to –57V for LTPoE ++ PSEs, relative to AGND.
Digital Power Supply
V
and draws a maximum of 15mA. A ceramic decoupling
cap of at least 0.1μF should be placed from V
as close as practical to each LTC4271 chip. A 1.8V core
voltage supply is generated internally and requires a 1μF
ceramic decoupling cap between the CAP1 pin and DGND.
26
EE
DD
requires a negative voltage of between –44V and
provides digital power for the LTC4271 processor,
2
DD
C/SMBus SDA pin.
requires 3.3V (nominally) relative to DGND.
2
C/SMBus bus. Isolation
DD
to DGND,
In the LTC4270/LTC4271, V
host controller’s non-isolated 3.3V supply. To maintain
required isolation AGND and DGND must not be con-
nected in any way.
Main PoE Power Supply
V
to the PDs. Because it supplies a relatively large amount
of power and is subject to significant current transients,
it requires more design care than a simple logic supply.
For minimum IR loss and best system efficiency, set V
near maximum amplitude (57V), leaving enough margin
to account for transient over or undershoot, temperature
drift, and the line regulation specifications of the particular
power supply used.
Bypass capacitance between AGND and V
portant for reliable operation. If a short circuit occurs at
one of the output ports it can take as long as 1μs for the
LTC4270 to begin regulating the current. During this time
the current is limited only by the small impedances in the
circuit and a high current spike typically occurs, causing a
voltage transient on the V
the LTC4270/LTC4271 to reset due to a UVLO fault. A 1μF ,
100V X7R capacitor placed near the V
electrolytic bulk capacitor of at least 47μF is recommended
to minimize spurious resets.
Serial Bus Isolation
The LTC4270/LTC4271 chipset uses transformers to isolate
the LTC4271 from the LTC4270. In this case, the SDAIN
and SDAOUT pins can be shorted to each other and tied
directly to the I
be 10BASE-T or 10/100BASE-T with a 1:1 turns ratio. It
is important that the selected transformers do not have
common-mode chokes. These transformers typically
provide 1500V of isolation between the LTC4271 and the
LTC4270. For proper operation strict layout guidelines
must be met.
EE
is the main isolated PoE supply that provides power
2
C/SMBus bus. The transformers should
EE
DD
supply and possibly causing
should be delivered by the
EE
pin along with an
EE
is very im-
42701f
EE