CY8C5365LTI-104 Cypress Semiconductor Corp, CY8C5365LTI-104 Datasheet - Page 9

• Manufacturer Part Number: CY8C5365LTI-104
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5365LTI-104

• Lead Free Status / Rohs Status: Compliant

3. Pin Descriptions
IDAC0, IDAC2. Low resistance output pin for high current DACs
(IDAC).
OpAmp0out, OpAmp2out. High current output of uncommitted
opamp
Extref0, Extref1. External reference input to the analog system.
OpAmp0-, OpAmp2-. Inverting input to uncommitted opamp.
OpAmp0+, OpAmp2+. Noninverting input to uncommitted
opamp.
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator
pin. If a crystal is not used then Xi must be shorted to ground and
Xo must be left floating.
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
SWDCK. Serial Wire Debug Clock programming and debug port
connection.
SWDIO. Serial Wire Debug Input and Output programming and
debug port connection.
SWV. Single Wire Viewer output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
Document Number: 001-66237 Rev. *A
Note
5. GPIOs with opamp outputs are not recommended for use with CapSense
[5]
.
Figure 2-4. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
[5]
.
Plane
Vssd
PRELIMINARY
Vddd
DDD
instead
Vssd
of from a V
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
of from a V
V
V
V
Requires a 1 µF capacitor to V
external use.
V
The two V
between them as short as possible, and a 1 µF capacitor to V
see
use.
V
regulator. V
device. All other supply pins must be less than or equal to
V
V
V
V
V
V
V
V
and must be less than or equal to V
XRES. External reset pin. Active low with internal pull-up.
BOOST
BAT
CCA
CCD
DDA
DDA
DDD
DDD
SSA
SSB
SSD
DDIO0
DDIO
PSoC
Vssa
Power System
. Battery supply to boost pump.
. Ground for all analog peripherals.
. Ground connection for boost pump.
. Ground for all digital logic and I/O pins.
. Output of analog core regulator and input to analog core.
. Output of digital core regulator and input to digital core.
. Supply for all analog peripherals and analog core
.
. Supply for all digital peripherals and digital core regulator.
must be less than or equal to V
must be tied to a valid operating voltage (2.7 V to 5.5 V),
, V
. Power sense connection to boost pump.
Vdda
DDIO1
DDIO
DDIO
CCD
DDA
®
, V
. Pins are Do Not Use (DNU) on devices without
. Pins are DNU on devices without USB.
5: CY8C53 Family Datasheet
pins must be shorted together, with the trace
must be the highest voltage present on the
DDIO2
on page 22. Regulator output not for external
Plane
Vssa
, V
DDIO3
. Supply for I/O pins. Each
SSA
DDA
. Regulator output not for
DDA
.
.
Page 9 of 106
DDD
instead
SSD
[+] Feedback
;