CY8C5367LTI-003 Cypress Semiconductor Corp, CY8C5367LTI-003 Datasheet - Page 39

• Manufacturer Part Number: CY8C5367LTI-003
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5367LTI-003

• Lead Free Status / Rohs Status: Compliant

7.2.3.16 Clock Generation
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
7.3 UDB Array Description
Figure 7-11
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
Figure 7-11. Digital System Interface Structure
7.3.1 UDB Array Programmable Resources
Figure 7-12
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
Document Number: 001-66237 Rev. *A
UDB
UDB
UDB
UDB
shows an example of a 16 UDB array. In addition to
shows an example of how functions are mapped into
HV
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B
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A
UDB
UDB
UDB
UDB
System Connections
System Connections
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B
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UDB
UDB
UDB
UDB
HV
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B
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A
PRELIMINARY
UDB
UDB
UDB
UDB
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B
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
Figure 7-12. Function Mapping Example in a Bank of UDBs
7.4 DSI Routing Interface Description
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
Figure 7-13
interconnect, which connects the UDB array routing matrix with
other device peripherals. Any digital core or fixed function
peripheral that needs programmable routing is connected to this
interface.
Signals in this category include:
8-Bit
Timer
I2C Slave
Interrupt requests from all digital peripherals in the system.
DMA requests from all digital peripherals in the system.
Digital peripheral data signals that need flexible routing to I/Os.
Digital peripheral data signals that need connections to UDBs.
Connections to the interrupt and DMA controllers.
Connection to I/O pins.
Connection to analog system digital signals.
UART
PSoC
UDB
UDB
UDB
UDB
Quadrature Decoder
®
illustrates the concept of the digital system
HV
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A
B
5: CY8C53 Family Datasheet
8-Bit SPI
UDB
UDB
UDB
UDB
HV
HV
B
A
Logic
12-Bit PWM
12-Bit SPI
UDB
UDB
UDB
UDB
16-Bit
PWM
HV
HV
A
B
16-Bit PYRS
Page 39 of 106
8-Bit
Timer
UDB
UDB
UDB
UDB
Logic
HV
HV
B
A
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