CY8C5367AXI-108 Cypress Semiconductor Corp, CY8C5367AXI-108 Datasheet - Page 41

• Manufacturer Part Number: CY8C5367AXI-108
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5367AXI-108

• Lead Free Status / Rohs Status: Compliant

Figure 7-17. I/O Pin Output Enable Connectivity
7.5.1 CAN Features
Document Number: 001-66237 Rev. *A
4 IO Control Signal Connections from
UDB Array Digital System Interface
CAN2.0A/B protocol implementation - ISO 11898 compliant
Listen Only mode
SW readable error counter and indicator
Sleep mode: Wake the device from sleep with activity on the
Rx pin
Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with
PIN 0
OE
Standard and extended frames with up to 8 bytes of data per
frame
Message filter capabilities
Remote Transmission Request (RTR) support
Programmable bit rate up to 1 Mbps
PIN1
OE
CAN Node 1
PSoC
CAN_H
En
CAN Transceiver
PIN2
OE
CAN Controller
Drivers
CAN
Tx Rx
PIN3
OE
CAN_L
Port i
PIN4
OE
PIN5
OE
Figure 7-18. CAN Bus System Implementation
PRELIMINARY
CAN Node 2
PIN6
OE
CAN_H
PIN7
OE
CAN_L
7.5 CAN
The CAN peripheral is a fully functional Controller Area Network
(CAN) supporting communication baud rates up to 1 Mbps. The
CAN controller implements the CAN2.0A and CAN2.0B
specifications as defined in the Bosch specification and
conforms to the ISO-11898-1 standard. The CAN protocol was
originally designed for automotive applications with a focus on a
high level of fault detection. This ensures high communication
reliability at a low cost. Because of its success in automotive
applications, CAN is used as a standard communication protocol
for motion oriented machine control networks (CANOpen) and
factory automation applications (DeviceNet). The CAN controller
features allow the efficient implementation of higher level
protocols
microcontroller CPU. Full configuration support is provided in
PSoC Creator.
the Philips PHY; the PHY is not included on-chip. The three
wires can be routed to any I/O
Enhanced interrupt controller
Receive path
PSoC
CAN receive and transmit buffers status
CAN controller error status including BusOff
16 receive buffers each with its own message filter
Enhanced hardware message filter implementation that
covers the ID, IDE and RTR
DeviceNet addressing support
Multiple receive buffers linkable to build a larger receive
message array
Automatic transmission request (RTR) response handler
Lost received message notification
CAN Bus
without
®
5: CY8C53 Family Datasheet
affecting
CAN Node n
CAN_H
the
CAN_L
performance
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