SCC2698BC1A84,512 NXP Semiconductors, SCC2698BC1A84,512 Datasheet - Page 18

• Manufacturer Part Number: SCC2698BC1A84,512
• Description: IC UART OCTAL ENHANCED 84-PLCC
• Manufacturer: NXP Semiconductors
• Type: Octal UARTr

Specifications of SCC2698BC1A84,512

• Number Of Channels: 8
• Package / Case: 84-LCC (J-Lead)
• Features: False-start Bit Detection
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 115.2 Kbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 30 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1120-5; 933976250512; SCC2698BC1A84

Philips Semiconductors
ISR[7] – MPI Change-of-State
This bit is set when a change-of-state occurs at the MPI1b, MPI0b,
MPI1a, MPI0a input pins. It is reset when the CPU reads the IPCR.
ISR[6] – Channel b Change in Break
This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command.
ISR[5] – Receiver Ready or FIFO Full Channel b
The function of this bit is programmed by MR1[6]. If programmed as
receiver ready, it indicates that a character has been received and is
waiting in the FIFO to be read by the CPU. It is set when the
character is transferred from the receive shift register to the FIFO
and reset when the CPU reads the receiver FIFO. If the FIFO
contains more characters, the bit will be set again after the FIFO is
read.
If programmed as FIFO full, it is set when a character is transferred
from the receive holding register to the receive FIFO and the
transfer causes the FIFO to become full, i.e., all three FIFO
positions are occupied. It is reset when FIFO is read and there is no
character in the receiver shift register. If there is a character waiting
in the receive shift register because the FIFO is full, the bit is set
again when the waiting character is transferred into the FIFO.
ISR[4] – Transmitter Ready Channel b
This bit is a duplicate of TxRDY (SR[2]).
ISR[3] – Counter Ready
In the counter mode of operation, this bit is set when the counter
reaches terminal count and is reset when the counter is stopped by
a stop counter command. It is initialized to ‘0’ when the chip is reset.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time the C/T reaches zero count). The bit
is reset by a stop counter command. The command, however, does
not stop the C/T.
ISR[2] – Channel a Change in Break
This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command.
ISR[1] – Receiver Ready or FIFO Full Channel a
The function of this bit is programmed by MR1[6]. If programmed as
receiver ready, it indicates that a character has been received and is
waiting in the FIFO to be ready by the CPU. It is set when the
character is transferred from the receive shift register to the FIFO
and reset when the CPU reads the receiver FIFO. If the FIFO
contains more characters, the bit will be set again after the FIFO is
read. If programmed as FIFO full, it is set when a character is
transferred from the receive holding register to the receive FIFO and
the transfer causes the FIFO to become full, i.e., all three FIFO
positions are occupied. It is reset when FIFO is read and there is no
character in the receiver shift register. If there is a character waiting
in the receive shift register because the FIFO is full, the bit is set
again when the waiting character is transferred into the FIFO.
ISR[0] – Transmitter Ready Channel a
This bit is a duplicate of TxRDY (SR[2]).
IMR – Interrupt Mask Register
The programming of this register selects which bits in the ISR cause
an interrupt output. If a bit in the ISR is a ‘1’ and the corresponding
2006 Aug 07
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
18
example. One can only program integer numbers in a digital divider.
bit in the IMR is a ‘1’, the INTRN output is asserted (Low). If the
corresponding bit in the IMR is a zero, the state of the bit in the ISR
has no effect on the INTRN output. Note that the IMR does not mask
reading of the ISR.
CTPU and CTPL – Counter/Timer Registers
The CTPU and CTPL hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which
may be loaded into the CTPU/CTPL registers is H‘0002’. Note that
these registers are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the C/T generates a
square wave with a period of twice the value (in clock periods) of
the CTPU and CTPL. The waveform so generated is often used for
a data clock. The formula for calculating the divisor n to load to the
CTPU and CTPL for a particular 1X data clock is shown below:
Often this division will result in a non-integer number; 26.3, for
Therefore, 26 would be chosen. This gives a baud rate error of
0.3/26.3 which is 1.14%; well within the ability asynchronous mode
of operation.
If the value in CTPU or CTPL is changed, the current half-period will
not be affected, but subsequent half-periods will be. The C/T will not
be running until it receives an initial ‘Start Counter’ command (read
at address A3–A0 = 1110). After this, while in timer mode, the C/T
will run continuously. Receipt of a subsequent start counter
command causes the C/T to terminate the current timing cycle and
to begin a new cycle using the values in the CTPU and CTPL.
The counter ready status bit (ISR[3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command read with
A3–A0 = H‘F’). The command, however, does not stop the C/T. The
generated square wave is output on MPO if it is programmed to be
the C/T output.
In the counter mode, the C/T counts down the number of pulses
loaded in CTPU and CTPL by the CPU. Counting begins upon
receipt of a start counter command. Upon reaching the terminal
count H‘0000’, the counter ready interrupt bit (ISR[3]) is set. The
counter continues counting past the terminal count until stopped by
the CPU. If MPO is programmed to be the output of the C/T, the
output remains High until the terminal count is reached, at which
time it goes Low. The output returns to the High state and ISR[3] is
cleared when the counter is stopped by a stop counter command.
The CPU may change the values of CTPU and CTPL at any time,
but the new count becomes effective only on the next start counter
command. If new values have not been loaded, the previous values
are preserved and used for the next count cycle.
In the counter mode, the current value of the upper and lower eight
bits of the counter (CTU, CTL) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent
potential problems which may occur if a carry from the lower eight
bits to the upper eight bits occurs between the times that both
halves of the counter is read. However, note that a subsequent start
counter command will cause the counter to begin a new count cycle
using the values in CTPU and CTPL.
n
2 x 16 Baud rate desired
C T Clock Frequency
SCC2698B
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