STPCD0175BTC3 STMicroelectronics, STPCD0175BTC3 Datasheet
STPCD0175BTC3
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STPCD0175BTC3 Summary of contents
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POWERFUL X86 PROCESSOR 64-BIT BUS ARCHITECTURE 64-BIT DRAM CONTROLLER SVGA GRAPHICS CONTROLLER UMA ARCHITECTURE VIDEO SCALER DIGITAL PAL/NTSC ENCODER VIDEO INPUT PORT CRT CONTROLLER 135MHz RAMDAC 3 LINE FLICKER FILTER SCAN CONVERTER PCI MASTER / SLAVE / ARBITER CTRL ISA ...
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STPC CONSUMER X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Can access up to 4GBytes of external memory. 8KByte unified instruction and data cache with write back and write through capability. Parallel processing integral floating ...
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PCI Controller Fully compliant with PCI 2.1 specification. Integrated PCI arbitration interface masters can connect directly. External PAL allows for greater than 3 masters. Translation of PCI cycles to ISA bus. Translation of ISA master initiated cycle ...
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STPC CONSUMER 4/51 Issue 1.2 ...
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UPDATE HISTORY FOR OVERVIEW. The following changes have been made to the Electrical Specification Chapter on the 02/02/2000. Section Change Text To check if your memory device is supported by the STPC, please refer to Added Table 9-3 Host ...
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... The STMicroelectronics x86 processor core is em- bedded with standard and application specific pe- ripheral modules on the same silicon die. The core has all the functionality of the STMicroelectronics standard x86 processor products, including the low power System Management Mode (SMM). System Management Mode (SMM) provides an ...
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The video output pipeline incorporates a video- scaler and color space converter function and pro- visions in the CRT controller to display a video window. While repainting the screen the CRT con- troller fetches both the video as well as ...
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GENERAL DESCRIPTION Figure 1-1 Functionnal description x86 Core Host I/F PCI m/s VIP Video pipeline 2D SVGA CRTC DRAM 8/51 ISA IPC EIDE PCI m/s Anti-Flicker Color Space Color Key Chroma HW Cursor Issue 1.2 ISA BUS EIDE PCI BUS ...
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Figure 1-2 Typical Application Super I/O Flash ISA MUX IRQ MUX DMA.REQ STPC Consumer DMA.ACK DMUX PCI 4x 16-bit EDO DRAMs Keyboard / Mouse Serial Ports Parallel Port Floppy RTC DMUX Issue 1.2 GENERAL DESCRIPTION 2x EIDE Monitor SVGA TV ...
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PIN DESCRIPTION 2. PIN DESCRIPTION 2.1 INTRODUCTION The STPC Consumer integrates most of the func- tionalities of the PC architecture result, many of the traditional interconnections between the host PC microprocessor and the peripheral devic- es are totally ...
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Table 2-2. Definition of Signal Pins Signal Name Dir BASIC CLOCKS AND RESETS SYSRSTI# I XTALI I XTALO I/O HCLK O DEV_CLK O GCLK2X I/O DCLK I/O PCI_CLKI I PCI_CLKO O SYSRSTO# O ISA_CLK O ISA_CLK2X O MEMORY INTERFACE MA[11:0] ...
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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir ISA/IDE COMBINED CONTROL IOCHRDY / DIORDY I/O ISA CONTROL OSC14M O ALE O BHE# I/O MEMR#, MEMW# I/O SMEMR#, SMEMW# O IOR#, IOW# I/O MASTER# I MCS16#, IOCS16# I ...
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Table 2-2. Definition of Signal Pins Signal Name Dir SDA / DDC[0] I/O COL_CMP O VIDEO INPUT VCLK I VIN I DIGITAL TV OUTPUT RED_TV, GREEN_TV, BLUE_TV O VCS O ODD_EVEN O CVBS O IREF1_TV I VREF1_TV I IREF2_TV I ...
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PIN DESCRIPTION 2.2 SIGNAL DESCRIPTIONS 2.2.1 BASIC CLOCKS AND RESETS SYSRSTI System Reset/Power good. This input is low when the reset switch is depressed. Other- wise, it reflects the power supply’s power good signal. SYSRSTI is asynchronous to all clocks, ...
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MD[63:0] Memory Data I/O. This is the 64-bit memory data bus. If only half of a bank is populat- ed, MD63-32 is pulled high, data is on MD31-0. MD[40-0] are read by the device strap option reg- isters during rising ...
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PIN DESCRIPTION driven by the target during data phase of read transactions. CBE#[3:0] Bus Commands/Byte Enables. These are the multiplexed command and byte enable signals of the PCI bus. During the address phase they define the command and during the ...
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LA[22]/SCS1# Unlatched Address (ISA)/Second- ary Chip Select (IDE) This pin has two functions, depending on whether the ISA bus is active or the IDE bus is active. When the ISA bus is active, this pins is ISA Bus unlatched address ...
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PIN DESCRIPTION 2.2.7 ISA/IDE COMBINED CONTROL IOCHRDY/DIORDY Channel Ready (ISA)/Busy/ Ready (IDE). This is a multi-function pin. When the ISA bus is active, this pin is IOCHRDY. When the IDE bus is active, this serves as IDE signal DI- ORDY. ...
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ISAOE# Bidirectional OE Control. This signal con- trols the OE signal of the external transceiver that connects the IDE DD bus and ISA SA bus. GPIOCS# I/O General Purpose Chip Select 1. This output signal is used by the external ...
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PIN DESCRIPTION ed to ISAOE# and the output is provided with a weak pull-up resistor. RTCRW# / DD[13] Real Time Clock RW. This pin is a multi-function pin. When ISAOE# is active, this signal is used as RTCRW#. This signal ...
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Table 2-3. Pinout. Pin # Pin name AF3 SYSRSTI A3 XTALI C4 XTALO G23 HCLK F25 DEV_CLK AF15 GCLK2X AF9 DCLK AD15 MA[0] AF16 MA[1] AC15 MA[2] AE17 MA[3] AD16 MA[4] AF17 MA[5] AC17 MA[6] AE18 MA[7] AD17 MA[8] AF18 ...
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PIN DESCRIPTION Pin # Pin name B21 PCI_GNT#[1] D20 PCI_GNT#[2] A5 PCI_INT[0] C6 PCI_INT[1] B4 PCI_INT[2] D5 PCI_INT[3] F2 LA[17]/DA[0] G4 LA[18]/DA[1] F3 LA[19]/DA[2] F1 LA[20]/PCS1# G2 LA[21]/PCS3# G3 LA[22]/SCS1# H2 LA[23]/SCS3# J4 SA[0] H1 SA[1] H3 SA[2] J2 SA[3] ...
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Pin # Pin name D18 VDD5 A22 VDD B14 VDD C9 VDD D6 VDD D11 VDD D16 VDD D21 VDD F4 VDD F23 VDD G1 VDD K23 VDD L4 VDD L23 VDD P2 VDD T4 VDD T23 VDD T26 VDD ...
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PIN DESCRIPTION 24/51 Issue 1.2 ...
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Update History for Pin Description chapter The following changes have been made to the Pin Description Chapter on 08/02/2000 Section Change Text Added Color Compare Signal 2.2 The following changes have been made to the Pin Description Chapter on ...
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Update History for Pin Description chapter 26/51 Issue 1.2 ...
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STRAP OPTION This chapter defines the STPC Consumer Strap Options and their location Memory Data Note Refer to Designation Lines MD0 1 MD1 - MD2 2 DRAM Bank 1 MD3 2 MD4 2 MD5 2 DRAM Bank 0 MD6 ...
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STRAP OPTION Memory Data Note Refer to Designation Lines MD38 - MD39 - MD40 CPU MD41 - MD42 - MD43 - Note; 1) This Strap Option selects between two different functional blocks, the first is the ISA (SMEMW#) and the ...
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Bit 1 This bit reflects the value sampled on MD[17] pin and controls the PCI clock output as follows: 0: PCI clock output = HCLK / 2 1: PCI clock output = HCLK / 3 Bit 0; Reserved This register ...
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ELECTRICAL SPECIFICATIONS 4. ELECTRICAL SPECIFICATIONS 4.1 Introduction The electrical specifications in this chapter are val- id for the STPC Consumer. 4.2 Electrical Connections 4.2.1 Power/Ground Connections/Decoupling Due to the high frequency of operation of the STPC Consumer necessary ...
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DC Characteristics Table 4-2. DC Characteristics Recommended Operating conditions : VDD = 3.3V Symbol Parameter Test conditio ns V Operating Voltage DD P Supply Power Internal Clock (Note 1) CLK V REF_D DAC Voltage Reference AC ...
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ELECTRICAL SPECIFICATIONS Figure 4-1 Drive Level and Measurement Points for Switching Characteristics CLK: B Valid OUTPUTS: Output n INPUTS: LEGEND Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - ...
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AC Timing parameters Table 4-4. PCI Bus AC Timing Name Parameter t1 PCI_CLKI to AD[31:0] valid t2 PCI_CLKI to FRAME# valid t3 PCI_CLKI to CBE#[3:0] valid t4 PCI_CLKI to PAR valid t5 PCI_CLKI to TRDY# valid T6 PCI_CLKI to ...
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ELECTRICAL SPECIFICATIONS Table 4-7. Video Input AC Timing Name Parameter t35 VIN[7:0] setup to VCLK t36 VIN[7:0] hold from VCLK t37 VCLK to ODD_EVEN valid t38 VCLK to VCS valid t39 ODD_EVEN setup to VCLK t40 ODD_EVEN hold from VCLK ...
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Update History for Electrical Specification chapter The following changes have been made to the Electrical Specification Chapter on the 07/02/2000. Section Change Text Timings t35 - t42 4.5 Revued The following changes have been made to the Electrical Specification ...
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Update History for Electrical Specification chapter 36/51 ...
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MECHANICAL DATA 5.1 388-Pin Package Dimension The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View ...
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MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols Min A 34.95 35.00 B 1.22 C 0.58 D 1.57 E 0.15 F 0.05 G 0.75 ...
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Figure 5-3. 388-pin PBGA Package - Dimensions C Solderball A Table 5-2. 388-pin PBGA Package - Dimensions Symbols Min A 0.50 B 1.12 C 0.60 D 0.52 E 0. Solderball after collapse G mm Typ ...
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MECHANICAL DATA 5.2 388-Pin Package thermal data 388-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Figure 5-4. 388-Pin PBGA structure Signal layers Figure 5-5. Thermal dissipation without heatsink Board ...
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Figure 5-6. Thermal dissipation with heatsink Board Ambient Rca Case Rjc Board Junction Rjb Board Rba Ambient Board dimensions: Junction - 10 12 layers (2 for signals, 1 GND, 1VCC The PBGA is ...
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MECHANICAL DATA 42/51 Issue 1.2 ...
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BOARD LAYOUT 6.1 THERMAL DISSIPATION Thermal dissipation of the STPC depends mainly on supply voltage result, when the system does not need to work at 3.3V, it may be to reduce the voltage to 3.15V for example. ...
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BOARD LAYOUT When considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-2. The ...
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Figure 6-4. Optimum layout for central ground ball The PBGA Package also dissipates heat through peripheral ground balls. When a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipation through the ...
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BOARD LAYOUT Figure 6-6. Bottom side layout and decoupling A local ground plane on opposite side of the board as shown in Figure 6-6 improves thermal dissipa- tion used to connect decoupling capacitances but can also be used ...
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HIGH SPEED SIGNALS Some Interfaces of the STPC run at high speed and have to be carefully routed or even shielded. Here is the list of these interfaces, in decreasing speed order: - Memory Interface. - Graphics and video ...
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... ORDERING DATA 7. ORDERING DATA 7.1 Ordering Codes STMicroelectronics Prefix Product Family PC: PC Compatible Product ID C01: Consumer Core Speed 66: 66MHz 75: 75MHz 80: 80MHz 10: 100MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial 0 to +70 C Tcase = 0 to +100 C I: Industrial -40 to +85 C Tcase = -40 to +100 C Operating Voltage ...
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Available Part Numbers Core Frequency Part Number (MHz) STPCC0166BTC3 66 STPCC0180BTC3 80 STPCC0110BTC3 100 STPCC0166BTI3 66 STPCC0180BTI3 80 Tcase Range CPU Mode ( +100 C DX2 DX - +100 C DX Issue ...
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ORDERING DATA 50/51 Issue 1.2 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics ...