STPCD01 STMicroelectronics, STPCD01 Datasheet
STPCD01
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STPCD01 Summary of contents
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PC Compatible Embedded Microprocessor POWERFUL X86 PROCESSOR 64-BIT 66MHz BUS INTERFACE 64-BIT DRAM CONTROLLER SVGA GRAPHICS CONTROLLER UMA ARCHITECTURE VIDEO SCALER VIDEO OUTPUT PORT VIDEO INPUT PORT CRT CONTROLLER 135MHz RAMDAC LINE FLICKER FILTER SCAN CONVERTER PCI ...
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STPC CLIENT X86 Processor core Fully static 32-bit 5-stage pipeline, x86 proc- essor with DOS, Windows and UNIX compat- ibility. Can access up to 4GB of external memory. KBytes unified instruction and data cache with write back and write through ...
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ISA master/slave The ISA clock generated from either 14.318MHz oscillator clock or PCI clock Supports programmable extra wait state for ISA cycles Supports I/O recovery time for back to back I/ O cycles. Fast Gate A20 and Fast reset. Supports ...
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STPC CLIENT 4/61 Issue 2.2 - October 13, 2000 ...
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UPDATE HISTORY FOR OVERVIEW The following changes have been made to the Board Layout Chapter on 02/02/2000. Section Change Text To check if your memory device is supported by the STPC, please refer to Added Table 6-69 Host Address to ...
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UPDATE HISTORY FOR OVERVIEW Section Change Text “Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers.” “Supports both legacy & native IDE modes” “Supports hard drives larger than 528MB” N/A Added “Support for CD-ROM and tape peripherals” “Backward compatibility ...
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... The STPC Client has in addition to the 5ST86 a Video subsystem and high quality digital Televi- sion output. The STMicroelectronics x86 processor core is em- bedded with standard and application specific pe- ripheral modules on the same silicon die. The core has all the functionality of the ST Microelectronics standard x86 processor products, including the low power System Management Mode (SMM) ...
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GENERAL DESCRIPTION scaled. Smooth interpolative scaling in both hori- zontal and vertical direction are implemented. Col- our and Chroma key functions are also imple- mented to allow mixing video stream with non-vid- eo frame buffer. The video output passes directly ...
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Figure 1-1. Functional description. x86 Core Host I/F PCI m/s VIP Video pipeline 2D SVGA CRTC DRAM GENERAL DESCRIPTION ISA IPC EIDE PCI m/s Anti-Flicker Colour Space Colour Key Chroma HW Cursor Issue 2.2 - October 13, 2000 ISA BUS ...
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GENERAL DESCRIPTION Figure 1-2. Pictorial Block Diagram Typical Application Super I/O Flash ISA MUX IRQ MUX DMA.REQ DMA.ACK DMUX PCI 4x 16-bit EDO DRAMs 10/61 Keyboard / Mouse Serial Ports Parallel Port Floppy RTC DMUX STPC Client STV0119 Issue 2.2 ...
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DESCRIPTION 2.1. INTRODUCTION The STPC Client integrates most of the functional- ities of the PC architecture result, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally assimilated to the STPC ...
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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir BASIC CLOCKS RESETS & XTAL SYSRSTI# I SYSRSTO#* O XTALI I XTALO I/O PCI_CLKI I PCI_CLKO O ISA_CLK O ISA_CLK2X O OSC14M* O HCLK* O DEV_CLK O GCLK2X* I/O ...
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Table 2-2. Definition of Signal Pins Signal Name Dir RTCRW#* / DD[13] I/O RTCDS#* / DD[12] I/O SA[19:8]* / DD[11:0] I/O SA[7:0] I/O SD[15:0]* I/O ISA/IDE COMBINED CONTROL IOCHRDY* / DIORDY I/O ISA CONTROL ALE* O BHE#* I/O MEMR#*, MEMW#* ...
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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir SDA / DDC[0]* I/O VIDEO INPUT VCLK* I VIN[7:0]* I DIGITAL TV OUTPUT TV_YUV[7:0]* O ODD_EVEN* O VCS* O MISCELLANEOUS ST[6:0] I/O CLKDEL[2:0]* I/O Note; * denotes theat the ...
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DESCRIPTIONS 2.2.1. BASIC CLOCKS RESETS & XTAL PWGD System Reset/Power good. This input is low when the reset switch is depressed. Other- wise, it reflects the power supply’s power good signal. PWGD is asynchronous to all clocks, and acts ...
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PIN DESCRIPTION 2.2.4. TV OUTPUT TV_YUV[7:0] Digital video outputs. ODD_EVEN Frame Synchronization . VCS Horizontal Line Synchronization . 2.2.5. PCI INTERFACE PCI_CLKI 33MHz PCI Input Clock This signal is the PCI bus clock input and should be driven from the ...
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LA[22]/SCS1# Unlatched Address (ISA) / Sec- ondary Chip Select (IDE) This pin has two func- tions, depending on whether the ISA bus is active or the IDE bus is active. When the ISA bus is active, this pin is ISA ...
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PIN DESCRIPTION 2.2.8. ISA CONTROL SYSRSTO# Reset Output to System. This is the system reset signal and is used to reset the rest of the components (not on Host Bus) in the system. The ISA bus reset is an externally ...
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ISAOE# Bidirectional OE Control. This signal con- trols the OE signal of the external transceiver that connects the IDE DD bus and ISA SA bus. GPIOCS# I/O General Purpose Chip Select 1. This output signal is used by the external ...
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PIN DESCRIPTION ISACLK and ISACLKX2 as the input selection strobes. DREQ_MUX[1:0] ISA Bus Multiplexed DMA Re- quest. These are the ISA bus DMA request sig- nals. They are to be encoded before connection to the STPC Client using ISACLK and ...
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Table 2-3. Pinout. Pin # Pin name AF3 PWGD AF15 XTALI AE16 XTALO G23 HCLK F25 DEV_CLK AC5 GCLK2X AD5 DCLK AF5 DCLK_DIR AD15 MA[0] AF16 MA[1] AC15 MA[2] AE17 MA[3] AD16 MA[4] AF17 MA[5] AC17 MA[6] AE18 MA[7] AD17 ...
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PIN DESCRIPTION Pin # Pin name C22 PCI_GNT#[0] B21 PCI_GNT#[1] D20 PCI_GNT#[2] D24 PCI_INT[0] C26 PCI_INT[1] A25 PCI_INT[2] B24 PCI_INT[3] F2 LA[17]/DA[0] G4 LA[18]/DA[1] F3 LA[19]/DA[2] F1 LA[20]/PCS1# G2 LA[21]/PCS3# G3 LA[22]/SCS1# H2 LA[23]/SCS3# J4 SA[0] H1 SA[1] H3 SA[2] ...
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Pin # Pin name A16 VDD5 B12 VDD5 B9 VDD5 D18 VDD5 A22 VDD B14 VDD C9 VDD D6 VDD D11 VDD D16 VDD D21 VDD F4 VDD F23 VDD G1 VDD K23 VDD L4 VDD L23 VDD P2 VDD ...
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PIN DESCRIPTION 24/61 Issue 2.2 - October 13, 2000 ...
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UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER The following changes have been made to the Pin Description Chapter on 11/02/2000 Section Change Text Signals AD[12:11] for internal use only. Not to be used for External PCI devic- “ Added 2.2.5. ...
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UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER Section Change Text “Note; 2.2.13. Added By setting signals ST[3:0] to the following value allows the STPC to be put Tristate. This means the STPC is switched off and no signals are being driven. ...
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Section Change Text “IOCS16# IO Chip Select16. This signal is the decode of the ISA bus SA15-0 address pins of without any qualification of the command signals. The STPC Client does not drive IOCS16# (similar to PC-AT design). An ISA ...
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UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER 28/61 Issue 2.2 - October 13, 2000 ...
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STRAP OPTION This chapter defines the STPC Client Strap Op- tions and their location Memory Data Refer to Designation Lines MD0 - Reserved MD1 - Reserved MD2 DRAM Bank 1 Speed MD3 Speed MD4 Type MD5 DRAM Bank 0 ...
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STRAP OPTION Memory Data Refer to Designation Lines MD38 - Reserved MD39 - Reserved MD40 - Reserved MD41 - Reserved MD42 - Reserved MD43 - Reserved Note 1; Setting of Strap Options MD [15:2] have no effect on the DRAM ...
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Bit Sampled Description Bit 7 SIMM 2 DRAM type Bits 6-5 SIMM 2 speed Bit 4 SIMM 3 dram type Bits 3-2 SIMM 3 speed Bit 1 Reserved Bit 0 Reserved Note that the SIMM speed and type information read ...
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ELECTRICAL SPECIFICATIONS 4. ELECTRICAL SPECIFICATIONS 4.1 INTRODUCTION The electrical specifications in this chapter are val- id for the STPC Client. 4.2 ELECTRICAL CONNECTIONS 4.2.1 POWER/GROUND CONNECTIONS/ DECOUPLING Due to the high frequency of operation of the STPC Client ...
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DC CHARACTERISTICS Table 4-2. DC Characteristics Recommended Operating conditions : VDD = 3.3V 0.3V, Tcase = 0 to 100 100 C (Industrial Range) unless otherwise specified Symbol Parameter V Operating Voltage operating voltage Note 3 DD5 ...
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ELECTRICAL SPECIFICATIONS Figure 4-1 Drive Level and Measurement Points for Switching Characteristics CLK: B Valid OUTPUTS: Output n INPUTS: LEGEND Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - ...
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POWER ON SEQUENCE tra tio ...
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ELECTRICAL SPECIFICATIONS 4.5.5 PCI AC TIMING CHARACTERISTICS Table 4-4. PCI Bus AC Timing Name Parameter t1 PCI_CLKI to AD[31:0] valid t2 PCI_CLKI to FRAME# valid t3 PCI_CLKI to CBE#[3:0] valid t4 PCI_CLKI to PAR valid t5 PCI_CLKI to TRDY# valid ...
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Figure 4-4 Memory Early Write Mode (ref table Table 4-5 ) tCMA CLK tCRP RAS# tCPN tCPN CAS# MA ROW MWE# MD Figure 4-5 EDO Read Mode (ref tableTable 4-5) tCRAS tCMA CLK tRP tRP tCRP RAS# CAS# MA Row ...
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ELECTRICAL SPECIFICATIONS Figure 4-6 EDO Write Mode (ref table Table 4-5 ) tCRAS tCMA CLK tRP tRP tCRP RAS# CAS# MA Row MWE# OPEN MD Figure 4-7 Fast Page Mode Read (ref table Table 4-5 ) tCRAS tCMD tCMA tCCAS ...
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Figure 4-8 Fast Page Mode Write (ref table Table 4-5 ) tCRAS tCMD tCMA tCCAS CLK tRAH tRAD tAR tCRP tDHR tCSH tRCD RAS# tWCS tDS tRC tRC tCPN tCPN tCAH tCWL tCPN tCPN CAS# MA ROW Column 1 MWE# ...
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ELECTRICAL SPECIFICATIONS Table 4-5. AC Memory Timing Characteristics Parameter tCRAS HCLK (or GCLK2X) to RAS#[3:0] valid (see Note 3) tCCAS HCLK (or GCLK2X) to CAS#[7:0] bus valid (see Note 3) tCMA HCLK (or GCLK2X) to MA[11:0] bus valid (see Note ...
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Table 4-6. Video Input/TV Output AC Timing Name Parameter t34 DCLK to TV_YUV[7:0] bus valid t35 VIN[7:0] setup to VCLK t36 VIN[7:0] hold from VCLK t37 VCLK to ODD_EVEN valid t38 VCLK to VCS valid t39 ODD_EVEN setup to VCLK ...
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ELECTRICAL SPECIFICATIONS 4.5.7 ISA INTERFACE AC TIMING CHARCTERISTICS Figure 4-10 ISA Cycle (ref tableTable 4-8) 2 ALE AEN Valid AENx 3 LA [23:17] Valid Address SA [19:0] CONTROL (Note 1) IOCS16# MCS16# IOCHRDY READ DATA WRITE DATA Note 1; Stands ...
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Table 4-8. ISA Bus AC Timing Name Parameter 4 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 4 11 XTALO to IOW# valid 4 11a Memory access to 16 bit ISA Slave - 2BCLK 4 11b Memory access to ...
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ELECTRICAL SPECIFICATIONS Table 4-8. ISA Bus AC Timing Name Parameter 4 24 IOR#, IOW# asserted before SA[19:0] 4 24o I/O access to 16 bit ISA Slave Standard cycle 4 24r I/O access to 16 bit ISA Slave Standard cycle 4 ...
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Table 4-8. ISA Bus AC Timing Name Parameter 4 38l I/O access to 8 bit ISA Slave Standard Cycle 4 41 SA[19:0] SBHE valid to IOCHRDY negated 4 41a Memory access to 16 bit ISA Slave 4 41b Memory access ...
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ELECTRICAL SPECIFICATIONS Table 4-8. ISA Bus AC Timing Name Parameter 4 64c SMEMW# negated to write data invalid - 16 bit 4 64d SMEMW# negated to write data invalid - 8 bit 4 64e IOW# negated to write data invalid ...
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MECHANICAL DATA 5.1 388-Pin Package Dimension The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View ...
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MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols Min A 34.95 35.00 B 1.22 1.27 C 0.58 0.63 D 1.57 1.62 E 0.15 0.20 ...
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Figure 5-3. 388-pin PBGA Package - Dimensions C Solderball A Table 5-2. 388-pin PBGA Package - Dimensions Symbols Min A 0.50 0.56 B 1.12 1.17 C 0.60 0.76 D 0.52 0.53 E 0.63 0.78 F 0.60 0.63 G 30.0 F ...
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MECHANICAL DATA 5.2 388-Pin Package thermal data 388-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Figure 5-4. 388-Pin PBGA structure Signal layers Figure 5-5. Thermal dissipation without heatsink Board ...
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Figure 5-6. Thermal dissipation with heatsink Board Ambient Rca Case Rjc Board Junction Rjb Board Rba Ambient Board dimensions: Junction - 10 12 layers (2 for signals, 1 GND, 1VCC) The PBGA is centered on ...
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MECHANICAL DATA 52/61 Issue 2.2 - October 13, 2000 ...
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BOARD LAYOUT 6.1 THERMAL DISSIPATION Thermal dissipation of the STPC depends mainly on supply voltage result, when the system does not need to work at 3.3V, it may be to reduce the voltage to 3.15V for example. ...
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BOARD LAYOUT When considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-2. The ...
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Figure 6-4. Optimum layout for central ground ball The PBGA Package also dissipates heat through peripheral ground balls. When a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipation through the ...
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BOARD LAYOUT Figure 6-6. Bottom side layout and decoupling A local ground plane on opposite side of the board as shown in Figure 6-6 improves thermal dissipa- tion used to connect decoupling capacitances but can also be used ...
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HIGH SPEED SIGNALS Some Interfaces of the STPC run at high speed and have to be carefully routed or even shielded. Here is the list of these interfaces, in decreasing speed order: - Memory Interface. - Graphics and video ...
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... ORDERING DATA 7. ORDERING DATA 7.1 ORDERING CODES STMicroelectronics Prefix Product Family PC: PC Compatible Product ID D01: Client Core Speed 66: 66MHz 75: 75MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial Case Temperature (Tcase +100 C I: Industrial Case Temperature (Tcase +100 C A: Auatomotive Case Temperature (Tcase +115 C Operating Voltage ...
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... AVAILABLE PART NUMBERS Core Frequency Part Number ( MHz ) STPCD0166BTC3 66 STPCD0175BTC3 75 STPCD0166BTI3 66 STPCD0175BTI3 75 STPCD0166BTA3 66 7.3 CUSTOMER SERVICE More information is available STMicroelectronics internet www.ST.com/STPC. CPU Mode Tcase Range ( DX / DX2 ) ( +100 - +100 - +115 C on the Any specific questions are to be addressed direct- ...
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ORDERING DATA 60/61 Issue 2.2 - October 13, 2000 ...
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... N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...