HD6412352F20 HITACHI, HD6412352F20 Datasheet
HD6412352F20
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HD6412352F20 Summary of contents
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... Hitachi 16-Bit Single-chip Microcomputer H8S/2357F-ZTAT ADE-602-146B Rev. 3.0 11/10/00 Hitachi, Ltd. H8S/2357 Series, H8S/2357 H8S/2352 H8S/2390 H8S/2392 H8S/2394 Hardware Manual TM ...
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... Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...
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... This manual describes the hardware of the H8S/2357 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes: 1. F-ZTAT (Flexible-ZTAT trademark of Hitachi, Ltd. 2. ZTAT is a trademark of Hitachi, Ltd. Preface ...
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...
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All pages of this manual 3 1.1 Overview 5 1.1 Overview 6 1.2 Block Diagram 9 1.3.1 Pin Arrangement 9 1.3.1 Pin Arrangement 12 1.3.2 Pin Functions in Each Operating Mode 15 ...
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204 7.2.5 DMA Band Control Register (DMABCR) 211 7.3.4 DMA Control Register (DMACR) 274 7.7 Usage Notes 352 9.8.2 Register Configuration 358 9.9.1 Overview 364 9.10.1 Overview 370 9.11.1 Overview 376 9.12.2 ...
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755 21.2.2 System Clock Control Register (SCKCR) All pages of Section 22 Electrical section 22 Characteristics 802 22.3.4 A/D Conversion Characteristics 808 22.4.2 DC Characteristics 813 22.4.3 AC Characteristics 817 22.4.4 A/D ...
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Section 1 Overview ........................................................................................................... 1.1 Overview............................................................................................................................ 1.2 Block Diagram................................................................................................................... 1.3 Pin Description................................................................................................................... 1.3.1 Pin Arrangement................................................................................................... 1.3.2 Pin Functions in Each Operating Mode................................................................ 11 1.3.3 Pin Functions ........................................................................................................ 16 Section 2 CPU ..................................................................................................................... 2.1 Overview............................................................................................................................ 23 2.1.1 Features................................................................................................................. 23 2.1.2 Differences ...
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Basic Timing...................................................................................................................... 62 2.9.1 Overview............................................................................................................... 62 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 62 2.9.3 On-Chip Supporting Module Access Timing....................................................... 64 2.9.4 External Address Space Access Timing............................................................... 65 Section 3 MCU Operating Modes 3.1 Overview............................................................................................................................ 67 3.1.1 Operating Mode Selection ...
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Trap Instruction ................................................................................................................. 90 4.6 Stack Status after Exception Handling .............................................................................. 91 4.7 Notes on Use of the Stack.................................................................................................. 91 Section 5 Interrupt Controller 5.1 Overview............................................................................................................................ 93 5.1.1 Features................................................................................................................. 93 5.1.2 Block Diagram...................................................................................................... 94 5.1.3 Pin Configuration ................................................................................................. 95 ...
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Bus Width Control Register (ABWCR) ............................................................... 126 6.2.2 Access State Control Register (ASTCR).............................................................. 127 6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 128 6.2.4 Bus Control Register H (BCRH) .......................................................................... 132 6.2.5 Bus Control Register L (BCRL)........................................................................... ...
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Write Data Buffer Function ............................................................................................... 183 6.10 Bus Release........................................................................................................................ 184 6.10.1 Overview............................................................................................................... 184 6.10.2 Operation .............................................................................................................. 184 6.10.3 Pin States in External Bus Released State ............................................................ 185 6.10.4 Transition Timing................................................................................................. 186 6.10.5 Usage Note ........................................................................................................... 187 6.11 Bus Arbitration................................................................................................................... ...
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Normal Mode........................................................................................................ 239 7.5.7 Block Transfer Mode............................................................................................ 242 7.5.8 DMAC Activation Sources................................................................................... 248 7.5.9 Basic DMAC Bus Cycles ..................................................................................... 251 7.5.10 DMAC Bus Cycles (Dual Address Mode) ........................................................... 252 7.5.11 DMAC Bus Cycles (Single Address Mode)......................................................... 260 7.5.12 Write ...
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Examples of Use of the DTC................................................................................ 305 8.4 Interrupts ............................................................................................................................ 307 8.5 Usage Notes ....................................................................................................................... 308 Section 9 I/O Ports ............................................................................................................. 309 9.1 Overview............................................................................................................................ 309 9.2 Port 1.................................................................................................................................. 313 9.2.1 Overview............................................................................................................... 313 9.2.2 Register Configuration ......................................................................................... 314 9.2.3 Pin ...
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Pin Functions ........................................................................................................ 367 9.10.4 MOS Input Pull-Up Function (H8S/2357 Only) .................................................. 369 9.11 Port D................................................................................................................................. 370 9.11.1 Overview............................................................................................................... 370 9.11.2 Register Configuration (H8S/2357 Only)............................................................. 371 9.11.3 Pin Functions ........................................................................................................ 373 9.11.4 MOS Input Pull-Up Function (H8S/2357 Only) .................................................. ...
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Basic Functions..................................................................................................... 437 10.4.3 Synchronous Operation ........................................................................................ 443 10.4.4 Buffer Operation................................................................................................... 445 10.4.5 Cascaded Operation .............................................................................................. 449 10.4.6 PWM Modes......................................................................................................... 451 10.4.7 Phase Counting Mode........................................................................................... 456 10.5 Interrupts ............................................................................................................................ 463 10.5.1 Interrupt Sources and Priorities ............................................................................ 463 10.5.2 DTC/DMAC ...
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Block Diagram...................................................................................................... 512 12.1.3 Pin Configuration ................................................................................................. 513 12.1.4 Register Configuration ......................................................................................... 513 12.2 Register Descriptions......................................................................................................... 514 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1).......................................................... 514 12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 514 12.2.3 Time ...
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Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 547 13.4 Interrupts ............................................................................................................................ 548 13.5 Usage Notes ....................................................................................................................... 548 13.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 548 13.5.2 Changing Value of CKS2 to CKS0 ...................................................................... ...
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Serial Mode Register (SMR) ................................................................................ 621 15.2.4 Serial Control Register (SCR) .............................................................................. 622 15.3 Operation ........................................................................................................................... 623 15.3.1 Overview............................................................................................................... 623 15.3.2 Pin Connections .................................................................................................... 624 15.3.3 Data Format .......................................................................................................... 625 15.3.4 Register Settings................................................................................................... 627 15.3.5 Clock..................................................................................................................... 629 15.3.6 Data ...
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Section 18 RAM ................................................................................................................... 673 18.1 Overview............................................................................................................................ 673 18.1.1 Block Diagram...................................................................................................... 673 18.1.2 Register Configuration ......................................................................................... 674 18.2 Register Descriptions......................................................................................................... 674 18.2.1 System Control Register (SYSCR)....................................................................... 674 18.3 Operation ........................................................................................................................... 675 18.4 Usage Note......................................................................................................................... 675 Section 19 ROM (H8S/2357 Only) ...
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Erase Mode........................................................................................................... 716 19.9.4 Erase-Verify Mode ............................................................................................... 716 19.10 Flash Memory Protection................................................................................................... 718 19.10.1 Hardware Protection............................................................................................. 718 19.10.2 Software Protection .............................................................................................. 718 19.10.3 Error Protection .................................................................................................... 719 19.11 Flash Memory Emulation in RAM .................................................................................... 721 19.11.1 Emulation in RAM ...
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Medium-Speed Mode......................................................................................................... 757 21.4 Sleep Mode ........................................................................................................................ 758 21.5 Module Stop Mode ............................................................................................................ 758 21.5.1 Module Stop Mode ............................................................................................... 758 21.5.2 Usage Notes .......................................................................................................... 759 21.6 Software Standby Mode..................................................................................................... 760 21.6.1 Software Standby Mode ....................................................................................... 760 21.6.2 Clearing Software ...
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A.2 Instruction Codes ............................................................................................................... 875 A.3 Operation Code Map.......................................................................................................... 890 A.4 Number of States Required for Instruction Execution....................................................... 894 A.5 Bus States During Instruction Execution........................................................................... 908 A.6 Condition Code Modification ............................................................................................ 922 Appendix B Internal I/O Register B.1 Addresses........................................................................................................................... 928 ...
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... Overview The H8S/2357 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space ...
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Table 1-1 Overview Item Specification General-register machine CPU Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 50 ...
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Item Specification 6-channel 16-bit timer on-chip 16-bit timer-pulse unit (TPU) Pulse I/O processing capability for pins' Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with TPU as time base Programmable pulse generator Output trigger selectable ...
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Item Specification Medium-speed mode Power-down state Sleep mode Module stop mode Software standby mode Hardware standby mode Eight MCU operating modes (F-ZTAT version) Operating modes Mode ...
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... Description — On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode 5 V version MHz MHz HD6412352F20 HD6412394F20* HD6412352TE20 HD6412394TE20* HD6412392F20 HD6412392TE20 HD6412390F20 HD6412390TE20 HD6432357(A**)F HD6432398(A**)F* HD6432357(A**)TE HD6432398(A**)TE* HD64F2357F20 HD64F2398F20* ...
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Block Diagram Figure 1-1 shows an internal block diagram of the H8S/2357 Series EXTAL XTAL STBY RES ) * 1 WDTOVF (FWE NMI PF /ø / /RD ...
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Pin Description 1.3.1 Pin Arrangement Figures 1-2 and 1-3 show the pin arrangement for the H8S/2357, and figures 1-4 and 1-5 show the pin arrangements for the H8S/2394, H8S/2392, and H8S/2390. SCK2 / ADTRG / P5 ...
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AV 103 CC V 104 ref AN0 / P4 105 0 AN1 / P4 106 1 AN2 / P4 107 2 AN3 / P4 108 3 AN4 / P4 109 4 AN5 / P4 110 5 DA0 / AN6 / ...
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SCK2 / ADTRG ref AN0 / AN1 / AN2 / AN3 / AN4 / ...
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AV 103 CC V 104 ref AN0 / P4 105 0 AN1 / P4 106 1 AN2 / P4 107 2 AN3 / P4 108 3 AN4 / P4 109 4 AN5 / P4 110 5 DA0 / AN6 / ...
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Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2357 Series in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. TFP-120 FP-128 Mode ...
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Pin No. TFP-120 FP-128 Mode IRQ6 IRQ7 /IRQ3/ 7 CS7 /IRQ2/ 6 CS6 — — 36 ...
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Pin No. TFP- FP- 120 128 Mode /SCK0 /SCK1 DREQ0 CS4 — — ...
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Pin No. TFP-120 FP-128 Mode EXTAL /ø HWR 84 92 LWR /LCAS/ 2 WAIT/ ...
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Pin No. TFP-120 FP-128 Mode 4 106 116 P1 /PO14/ 6 TIOCA2 107 117 P1 /PO13/ 5 TIOCB1/ TCLKC 108 118 P1 /PO12/ 4 TIOCA1 109 119 P1 /PO11/ 3 TIOCD0/ TCLKB 110 120 P1 /PO10/ 2 TIOCC0/ TCLKA 111 ...
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Pin Functions Table 1-3 outlines the pin functions of the H8S/2357 Series. Table 1-3 Pin Functions Type Symbol Power Internal voltage step-down drop pin Clock XTAL EXTAL ø 16 Pin No. ...
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Type Symbol Operating mode control MD 0 RES System control STBY BREQ BREQO BACK Pin No. TFP-120 FP-128 I/O 115 to 125 to Input 113 123 73 81 Input 75 83 Input 88 96 Input 86 94 ...
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Type Symbol 2 System control FWE* Interrupts NMI IRQ7 to IRQ0 Address bus Data bus CS7 to Bus control CS0 AS RD HWR LWR 18 Pin No. TFP-120 FP-128 I/O ...
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Type Symbol CAS Bus control WAIT LCAS DREQ1, DMA controller DREQ0 (DMAC) TEND1, TEND0 DACK1, DACK0 16-bit timer- TCLKD to pulse unit TCLKA (TPU) TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 Pin No. TFP-120 FP-128 ...
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Type Symbol 16-bit timer- TIOCA4, pulse unit TIOCB4 (TPU) TIOCA5, TIOCB5 Programmable PO15 to pulse generator PO0 (PPG) 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 WDTOVF* 3 Watchdog timer (WDT) Serial TxD2, communication TxD1, interface (SCI) TxD0 Smart Card ...
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Type Symbol A/D converter AV CC and D/A converter ref I/O ports ...
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Type Symbol I/O ports ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate 8/16/32-bit register-register add/subtract : 8-bit register-register multiply 16 8-bit register-register divide 16 16-bit register-register multiply 32 16-bit register-register divide CPU operating mode Advanced ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit expanded registers, and one 8-bit control register, have been added. Expanded address space Advanced ...
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CPU Operating Modes The H8S/2357 Series CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
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Address Space Figure 2-3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'00000000 H'00FFFFFF H'FFFFFFFF Program area Cannot be used by the ...
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Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2-4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU ...
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Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set hardware at the start of an exception- handling sequence. ...
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The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: ...
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Memory Data Formats Figure 2-8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* LDM, STM MOVFPE, MOVTPE* Arithmetic ...
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Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes Function Instruction Data MOV BWL BWL transfer POP, PUSH — — ...
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Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General register* ERn General ...
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Table 2-3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM 40 1 Size* Function B/W/L (EAs) Rd, Rs Moves data between two general registers or between a general register and memory, or moves ...
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Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU 1 Size* Function B/W Rd, Rd Performs addition or subtraction on data in two general registers immediate data and ...
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Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS 42 1 Size* Function B Performs signed division on data in two general registers: either 16 bits remainder or 32 bits bit remainder. B/W/L Rd – Rs, ...
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Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR 1 Size* Function B/W Rd, Rd Performs a logical AND operation on a general register and another general register or ...
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Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR 44 1 Size* Function B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified ...
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Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST 1 Size* Function B C (<bit-No.> of <EAd>) Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the ...
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Type Instruction Branch Bcc instructions JMP BSR JSR RTS 46 1 Size* Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ ...
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Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP 1 Size* Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. — Causes a transition to a power-down state. B/W (EAs) CCR, (EAs) ...
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Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction ...
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Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2-9 shows ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed ...
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Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
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If an odd address is specified in word or longword memory access branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding ...
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Table 2-6 Effective Address Calculation 54 ...
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55 ...
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56 ...
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Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-11 shows a diagram of the processing states. Figure 2-12 indicates the state ...
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End of bus request Bus-released state End of exception handling Exception-handling state RES = high *1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition ...
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Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table ...
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Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI pin is high, ...
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Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Note: *Ignored when returning. Figure 2-13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released ...
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Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared sleep mode, CPU operations stop immediately after ...
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Internal address bus Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Figure 2-14 On-Chip Memory Access Cycle ø Address bus AS RD HWR, LWR Data bus High-impedance state Figure 2-15 Pin ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-16 shows the access ...
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... TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection (F-ZTAT™ Version) The H8S/2357 has eight operating modes (modes 10, 11, 14 and 15). These modes are determined by the mode pin (MD operating mode and ...
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Modes are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can ...
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The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2357 Series actually accesses a maximum of 16 Mbytes. Modes are externally expanded modes that allow access to external memory and peripheral devices. The external ...
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Register Descriptions 3.2.1 Mode Control Register (MDCR) Bit : 7 — Initial value : 1 R/W : — Note: * Determined by pins MD MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2357 ...
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Bit 5 Bit 4 Interrupt Control INTM1 INTM0 Mode — — Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description 0 An interrupt ...
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Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19, ROM. Bit 3 FLSHE Description 0 Flash control registers are not selected for addresses ...
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Mode 6 (H8S/2357 Only) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B and C function as input ports immediately after a reset. They can each be set to ...
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Modes 12 and 13 (F-ZTAT Version Only) Modes 12 and 13 are not supported in the H8S/2357 Series, and must not be set. 3.3.10 Mode 14 (F-ZTAT Version Only) This is a flash memory user program mode. For details, ...
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Pin Functions in Each Operating Mode The pin functions of ports vary depending on the operating mode. Table 3-4 shows their functions in each operating mode. Table 3-4 Pin Functions in Each Mode Mode Port 4 ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *3 On-chip RAM External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External addresses ...
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Mode 10* (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'020000 External address H'FFDC00 On-chip RAM External address H'FFFC00 H'FFFE40 I/O registers H'FFFF08 External address H'FFFF28 I/O registers H'FFFFFF Notes: 1. External ...
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Mode 14* User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'020000 External address H'FFDC00 On-chip RAM External address H'FFFC00 H'FFFE40 I/O registers H'FFFF08 External address H'FFFF28 I/O registers H'FFFFFF ...
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H'000000 H'FFDC00 H'FFEC00 H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF Notes: 1. This is a reserved space. Access to this space is inhibited. The space can be made available for use as an external address space by clearing the RAME bit of ...
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Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-3 Memory Map in Each Operating Mode (H8S/2392) 80 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address ...
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Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-4 Memory Map in Each Operating Mode (H8S/2394) Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or ...
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Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits ...
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Table 4-2 Exception Vector Table Exception Source Power-on reset 3 Manual reset* Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 ...
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Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2357 Series enters the reset state. A reset initializes the internal state of the CPU and the registers ...
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Table 4-3 Reset Types Reset Transition Conditions RES Type NMI Power-on reset High Low Manual reset* Low Low A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset*. ...
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RES Address bus RD HWR, LWR (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If ...
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NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, ...
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Table 4-5 Status of CCR and EXR after Trap Instruction Exception Handling Interrupt Control Mode 0 2 Legend 1: Set Cleared to 0 —: Retains value prior to execution. 4.6 Stack Status after Exception Handling Figure 4-4 ...
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Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting odd value may lead to a malfunction. Figure 4-5 shows an example of what happens when the ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2357 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features: Two interrupt control modes Any of two interrupt control modes can be set by ...
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Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input ISCR Internal interrupt request WOVI to TEI Interrupt controller Legend : IRQ sense control ...
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Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests 5.1.4 Register Configuration Table 5-2 summarizes the registers ...
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Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 ...
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Interrupt Priority Registers (IPRA to IPRK) Bit : 7 — Initial value : 0 R/W : — The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels for interrupts other than ...
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As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets the priority of the ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 R/W : R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB ...
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IRQ Status Register (ISR) Bit : 7 IRQ7F Initial value : 0 R/W : R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be ...
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Figure 5-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant ...
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Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) CMI (compare match) Reserved ADI (A/D conversion end) Reserved TGI0A (TGR0A input ...
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Interrupt Source TGI1A (TGR1A input capture/ compare match) TGI1B (TGR1B input capture/ compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/ compare match) TGI2B (TGR2B input capture/ compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A ...
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Interrupt Source CMIA0 (compare match A0) CMIB0 (compare match B0) OVI0 (overflow 0) Reserved CMIA1 (compare match A1) CMIB1 (compare match B1) OVI1 (overflow 1) Reserved DEND0A (channel 0/channel 0A transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/channel ...
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Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2357 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. ...
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Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. ...
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Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority ...
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Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, ...
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IRQ0 Yes Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in 110 Program execution status Interrupt generated? Yes Yes NMI No I=0 Yes No IRQ1 Yes Save PC and CCR I 1 Read vector address Branch to interrupt handling ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5-6 shows a ...
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Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in 112 Program execution status No Interrupt generated? Yes Yes NMI Level 6 interrupt? No Yes No Mask ...
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Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Figure 5-7 Interrupt Exception Handling 114 ...
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Interrupt Response Times The H8S/2357 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM* and the stack area in on-chip RAM, enabling high- speed processing. Table 5-9 shows ...
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Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is ...
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Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is ...
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DTC and DMAC Activation by Interrupt 5.6.1 Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: Interrupt request to CPU Activation request to DTC Activation request to DMAC Selection ...
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Operation The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected ...
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Table 5-11 Interrupt Source Selection and Clearing Control Settings DMAC DTC DTA DTCE Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt ...
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Section 6 Bus Controller 6.1 Overview The H8S/2357 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle Write buffer ...
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Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS0 to CS7 External bus control signals BREQ BACK BREQO WAIT External DRAM signals Figure 6-1 Block Diagram of Bus Controller Area decoder ABWCR ASTCR BCRH BCRL ...
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Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Name Address strobe Read High write/write enable Low write Chip select 0 Chip select 1 Chip select 2/row address strobe 2 Chip select ...
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Name Upper column address strobe Lower column strobe Wait Bus request Bus request acknowledge Bus request output 6.1.4 Register Configuration Table 6-2 summarizes the registers of the bus controller. Table 6-2 Bus Controller Registers Name Bus width control register Access ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 Modes Initial value : 1 R/W : R/W Mode 4 Initial value : 0 R/W : R/W ABWCR is an 8-bit readable/writable register that ...
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Access State Control Register (ASTCR) Bit : 7 AST7 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal ...
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Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space ...
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
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Bus Control Register H (BCRH) Bit : 7 ICIS1 Initial value : 1 R/W : R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to ...
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Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states Bit 3—Burst Cycle Select 0 (BRSTS0): Selects ...
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Bus Control Register L (BCRL) Bit : 7 BRLE BREQOE Initial value : 0 R/W : R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the LCAS signal, DMAC single address transfer, ...
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Bit 5 EAE Description 0 Addresses H'010000 to H'01FFFF are in on-chip ROM 1 Addresses H'010000 to H'01FFFF are external addresses (external expansion mode reserved area* (single-chip mode) Note: * Reserved areas should not be accessed. Bit 4—LCAS ...
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Memory Control Register (MCR) Bit : 7 TPC Initial value : 0 R/W : R/W MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and ...
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Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas are designated as 8-bit DRAM space, and 0 otherwise. Bit 4 CW2 Description 0 16-bit DRAM space selected 1 8-bit DRAM space selected Bits 3 ...
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DRAM Control Register (DRAMCR) Bit : 7 RFSHE Initial value : 0 R/W : R/W DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized ...
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Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR. Bit 4 ...
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Refresh Timer/Counter (RTCNT) Bit : 7 Initial value : 0 R/W : R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare ...
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Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 2-Mbyte units, and performs bus control for external space in area units. Figure ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
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Table 6-3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL ABWCR ASTCR ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The H8S/2357 Series memory interfaces comprise a basic ...
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Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on ...
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Chip Select Signals The H8S/2357 Series can output chip select signals (CS0 to CS7) to areas the signal being driven low when the corresponding external space area is accessed. Figure 6-3 shows an example of CSn ...
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Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment ...
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Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D for accesses. The amount of data that can be accessed at one time is one byte ...
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Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data bus write, ...
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Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states cannot be ...
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Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states can be inserted. ø Address ...
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Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D for the even address, and the lower half (D Wait states cannot ...
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Address bus CSn Read HWR LWR Write Note Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) ...
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Address bus CSn Read HWR LWR Write Note Figure 6-10 Bus Timing ...
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Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D for the even address, and the lower half (D Wait states ...
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Address bus CSn Read HWR LWR Write Note Figure 6-12 Bus Timing ...
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Address bus CSn Read HWR LWR Write Note Figure 6-13 Bus Timing ...
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Wait Control When accessing external space, the H8S/2357 Series can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin w wait insertion ...
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Figure 6-14 shows an example of wait state insertion timing. ø WAIT Address bus AS RD Read Data bus HWR, LWR Write Data bus Note: indicates the timing of WAIT pin sampling. Figure 6-14 Example of Wait State Insertion Timing ...
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DRAM Interface 6.5.1 Overview When the H8S/2357 Series is in advanced mode, external space areas can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the ...
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Data Bus If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as ...
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Basic Timing Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and ...
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Precharge State Control When DRAM is accessed, RAS precharging time must be secured. With the H8S/2357 Series, one T state is always inserted when DRAM space is accessed. This can be changed to two T p setting the TPC ...
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Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion When the bit in ASTCR corresponding to an area designated ...
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WAIT Address bus C Sn (RAS) CAS Read Data bus CAS Write Data bus indicates the timing of WAIT pin sampling. Notes Figure 6-17 Example of Wait State Insertion Timing (CW2 = 1, 8-Bit ...
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Byte Access Control When DRAM with a 16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. When the CW2 bit is cleared MCR, the 2-CAS system is ...
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H8S/2357 Series (Address shift size set to 9 bits) Figure 6-19 Example of 2-CAS System Connection 166 256-kbyte x 16-bit configuration CS (RAS) CAS LCAS HWR (WE ...
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Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number ...
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RAS Down Mode and RAS Up Mode Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal ...
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RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed ...
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Refresh Control The H8S/2357 Series is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. (1) CAS-before-RAS (CBR) Refreshing To select CBR refreshing, set the RFSHE bit in ...
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RTCNT RTCOR Refresh request signal and CMF bit setting signal ø CS (RAS) CAS, LCAS When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be ...
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T Rp ø CSn (RAS) CAS, LCAS Figure 6-26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. ...
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DMAC Single Address Mode and DRAM Interface When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the ...
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When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the T interface. In modes other than DMAC single address mode, burst ...
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Burst ROM Interface 6.7.1 Overview With the H8S/2357 Series, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access ...
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T 1 ø Address bus CS0 AS RD Data bus Figure 6-30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) 176 Full access Only lower address changed Read data ...
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Address bus CS0 AS RD Data bus Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion ...