AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 71

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8. Instruction Cycle Summary
8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.2
8.2.3
32002F–03/2010
Definitions
Special considerations
Issue
Issue latency
PC as destination register
Alignment of change-of-flow targets
Memory and bus timings
This chapter presents the instructions in AVR32UC CPU, and the number of clock cycle they
require to complete. All the instructions in each group behave similarly in the pipeline. The final
subchapter presents code examples to illustrate the clock cycle requirements of various code
constructs.
The following definitions are presented in the tables below:
An instruction is issued when it leaves the ID stage and enters the EX stage.
The issue latency represents the number of clock cycles required between the issue of the
instruction and the issue of the following instruction. For some change-of-flow instructions, this
includes the cycle penalty caused by the pipeline flush. The issue latency assumes, unless
stated otherwise, that the instruction and data memories are able to return an instruction or data
in a single cycle, which may not be true for slow program memories or data memories mapped
on the HSB bus.
Most instructions can take PC as destination register. This will result in a jump to the calculated
address. The jump is performed when the instruction writing to PC has completed, and all other
effects of the instruction, like updating of pointer registers for load instructions with PC as target
instruction, have been committed. Instructions writing to PC will have an additional issue latency
of 2 cycles due to the pipeline flush.
The cycle count number for change-of-flow instructions assumes that the target instruction is a
compact instruction or word-aligned extended instruction. An extra cycle will be required if the
target instruction is a halfword-aligned extended instruction, since both halves of the instruction
must be fetched before it can be issued.
Performance of memory accesses and instruction fetching are affected by the performance of
system memories and system bus. The following are examples of factors that may affect the
cycle count of such operations:
• Accesses to the IRAM section in parallel with another bus master, for example a DMA
• Accesses to memories with wait states, for example flash or external memories.
• Using system buses with wait states or arbitration overhead.
• Accesses to memories that are simultaneously being accessed by other bus masters.
controller.
AVR32
71