AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 9

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
SS - Secure State
DM - Debug State Mask
D - Debug State
M2, M1, M0 - Execution Mode
Figure 2-3.
This bit is indicates if the processor is executing in the secure state. Only implemented in
devices implementing revision 3 of the AVR32 architecture, set to 0 in older revisions. The bit is
initialized in an IMPLEMENTATION DEFINED way at reset. Refer to
on page 59
If this bit is set, the Debug State is masked and cannot be entered. The bit is cleared at reset,
and can both be read and written by software.
The processor is in debug state when this bit is set. The bit is cleared at reset and should only be
modified by debug hardware, the breakpoint instruction or the retd instruction. Undefined behav-
iour may result if the user tries to modify this bit using other mechanisms.
These bits show the active execution mode. The settings for the different modes are shown in
Table 2-1 on page
supervisor mode after reset. These bits are modified by hardware when initiating interrupt or
exception processing. Execution of the scall, rets or rete instructions will also change these bits.
Undefined behaviour may result if the user tries to modify these bits using the mtsr, ssrf or csrf
instructions. If software needs to change these bits, scall, rets or rete should be used, possibly
with prior modifications of the stack, to achieve the desired changes in a safe way. Refer to the
AVR32 Architecture Manual for the behaviour of these instructions, note especially how the
stack is modified after their execution.
Bit 15
0
-
T
0
0
-
for more information.
The Status Register low halfword
0
-
10. M2 and M1 are cleared by reset while M0 is set so that the processor is in
0
-
0
-
0
-
0
-
0
-
0
-
L
0
Q
0
V
0
N
0
Z
0
Bit 0
C
0
Section 5. ”Secure State”
Bit name
Initial value
Carry
Zero
Sign
Overflow
Saturation
Lock
Reserved
Scratch
Reserved
AVR32
9