AT83EB5114 Atmel Corporation, AT83EB5114 Datasheet - Page 63

• Manufacturer Part Number: AT83EB5114
• Manufacturer: Atmel Corporation

Specifications of AT83EB5114

• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 11
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 50
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Operating Voltage (vcc): 3.0 to 3.6
• Timers: 4
• Mask Rom (kbytes): 4
• Watchdog: Yes

How to Take Advantage of the Calibration Value
Example
Assembler code example
Registers
4311C–8051–02/08
The coefficient stored on the stacked die allow to determine the conversion result the
AT8xEB5114 should have returned in case its Vref was exactly equal to 2.4V. In order to
determine it, a multiplication of the result of the conversion with the coefficient stored in
the stack, followed by a shift are sufficient.
Vref is 2.36V instead of 2.4V, and only 8 bits are necessary.
The value measured during the test 2.36V. So, in accordance with the Table 47, the
coefficient which has to be stored on the EEPROM is 0x7e which corresponds to
0.1111110 in binary, which also corresponds to around 2.36/2.4.
If, for example, after a conversion, the ADDH register contains 0xf0, to know the result
the ADC should have returned in case the Vref was really at 2.4V, the following opera-
tions are necessary:
0xf0 * 0x7e = 1111 0000 * 0111 1110 = 0x7620 = 0111 0110 0010 0000.
So because of the point on the coefficient, the result is 1110 110 which is 0xec.
This is an example of assembler code optimized for size and fast recalculation in case 8
bits are sufficient.
The new result is stored on the accumulator.
This routine requires 15 bytes + 3 bytes for the long call (LCALL).
The execution of the subroutine (including the LCALL) is 18 cycles in normal case and
19 cycles in case of overflow (less than 10us with a 12 MHz oscillator and the X2 mode).
Table 48. ADCON Register
ADCON (S:F3h)
ADC Control Register
QUIETM
Number
start_adjustement :
end_adjustement
Bit
7
7
6
Mnemonic Description
PSIDLE
QUIETM
PSIDLE
Bit
6
Quiet mode (best precision)
Set to put in quiet mode during conversion.
Cleared by hardware after completion of the conversion.
Pseudo Idle mode (good precision)
Set to put in idle mode during conversion.
Cleared by hardware after completion of the conversion.
:
ADEN
MOV
MOV
MUL
RLC
MOV
RLC
JNC
MOV
RET
5
B,coeff ; Coeff
A,ADDH
AB
A
A,B
A
end_fix ; Result OK
A,#0ffh ; Overflow
ADEOC
4
; ADC result
;
; Recover lowest bit
;
; Recover result
ADSST
3
SCH2
2
SCH1
1
SCH0
0
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