AT83EB5114 Atmel Corporation, AT83EB5114 Datasheet - Page 74

• Manufacturer Part Number: AT83EB5114
• Manufacturer: Atmel Corporation

Specifications of AT83EB5114

• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 11
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 50
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Operating Voltage (vcc): 3.0 to 3.6
• Timers: 4
• Mask Rom (kbytes): 4
• Watchdog: Yes

Status of the Flash Memory
Loading the Column Latches
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AT89/83EB5114
The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY
is set when programming is in progress.
Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This
provides the capability to program the whole memory by byte, by page or by any number
of bytes in a page.
When programming is launched, an automatic erase of the locations loaded in the col-
umn latches is first performed, then programming is effectively done. Thus no page or
block erase is needed and only the loaded data are programmed in the corresponding
page.
The following procedure is used to load the column latches and is summarized in
Figure 34:
Figure 34. Column Latches Loading Procedure
Note:
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–
–
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Disable interrupt and map the column latch space by setting FPS bit.
Load the DPTR with the address to load.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
If needed loop the three last instructions until the page is completely loaded.
unmap the column latch and Enable Interrupt
The last page address used when loading the column latch is the one used to select the
page programming address.
Column Latches Mapping
Column Latches Loading
Exec: MOVX @DPTR, A
Data memory Mapping
DPTR= Address
ACC= Data
Data Load
Last Byte
Disable IT
to load?
Enable IT
FPS= 1
FPS= 0
EA= 1
EA= 0
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